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[VHDL-FPGA-Verilog] Verilog--shiyanbaogao

Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
Platform: | Size: 15360 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] VGA-VerilogHDL

Description: 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
Platform: | Size: 141312 | Author: liping | Hits:

[VHDL-FPGA-Verilog] c18_divider

Description: 精通verilog HDL语言编程源码之4--常用除法器设计-Proficient in language programming verilog HDL source of 4- Common divider design
Platform: | Size: 1024 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] 4weishuzipinlvjikongzhimokuai

Description: Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
Platform: | Size: 3072 | Author: 李少洋 | Hits:

[VHDL-FPGA-Verilog] 16_FIR

Description: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Platform: | Size: 799744 | Author: yuming | Hits:

[Crack Hack] lfsr

Description: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[VHDL-FPGA-Verilog] Verilog_HDL

Description: Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive account of lexical, syntax.
Platform: | Size: 9274368 | Author: 李立 | Hits:

[VHDL-FPGA-Verilog] mult_piped_8x8

Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] div16

Description: 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
Platform: | Size: 3072 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] mcst

Description: 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
Platform: | Size: 1024 | Author: yy | Hits:

[Software Engineering] fre_ctrl

Description: 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL description of the behavior and structure of a description of the realization of frequency meter 8, 4 0 detection circuit principle of the amendment note
Platform: | Size: 14336 | Author: 黎明 | Hits:

[VHDL-FPGA-Verilog] VerilogHDLDigitalControlSystemExample

Description: 《Verilog HDL数字控制系统设计实例》-冼进-源代码- Verilog HDL Digital Control System Design - Xian Jin- source code
Platform: | Size: 11381760 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilog] multiply

Description: Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] divide

Description: Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved. 2. support angle recored algorithm.-cordic IC implement for fast cordic calculate.Including test bench.feature: 1. slicon proved.2. support angle recored algorithm.
Platform: | Size: 8192 | Author: TTC | Hits:

[VHDL-FPGA-Verilog] Verilog-book

Description: 学习Verilog语言必备资料，包括语法总结 编写Verilog HDL 源代码的标准及设计流程-Verilog language learning essential information, including syntax summary of Verilog HDL source code for the preparation of standards and design process
Platform: | Size: 3835904 | Author: shaoyqo | Hits:

[Speech/Voice recognition/combine] speech

Description: 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
Platform: | Size: 3072 | Author: ji | Hits:

[VHDL-FPGA-Verilog] led_display

Description: 基于Verilog HDL的流水灯程序设计-Verilog HDL-based design flow lights
Platform: | Size: 7168 | Author: 蓝色的海 | Hits:
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