rece_7E HDLC control began to receive data to the - CodeBus

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Title: rece_7E

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1.91kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
lscql

Description: HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language

Downloaders recently: [More information of uploader lscql]

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