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[Other] Verilog.HDL.A.Guide.To.Digital.Design.And.Synthesi

Description: VHDL的数字设计与综合的经典图书，与大家共享-VHDL digital design and synthesis of the classic books, and share
Platform: | Size: 1723392 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] adder_ahead8bit

Description: 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
Platform: | Size: 10240 | Author: 剑指眉梢 | Hits:

[VHDL-FPGA-Verilog] risc_spm

Description: advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
Platform: | Size: 4096 | Author: zhenglao | Hits:

[VHDL-FPGA-Verilog] verilogfifo

Description: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Platform: | Size: 1024 | Author: zzm | Hits:

[Other] chinese_VerilogHDL

Description: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模，想学习的这个资料对你有用。-Verilog HDL is a hardware description language, for the algorithm level, gate-level to switch-level abstract design of the multiple levels of system modeling, want to study this information be useful to you.
Platform: | Size: 32768 | Author: 刘斐 | Hits:

[Other] VerilogHDL_book

Description: Verilog HDL硬件描述语言，徐振林编著。pdf格式。-Verilog HDL Hardware Description Languages, edited cheng. Pdf format.
Platform: | Size: 4841472 | Author: Zhou | Hits:

[VHDL-FPGA-Verilog] cpldPWM

Description: verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
Platform: | Size: 236544 | Author: 章风 | Hits:

[VHDL-FPGA-Verilog] VerilogHDLchinapub

Description: Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Description Language Introduction 01. PDF 02HDL Guide. PDF 0 3 language elements. PDF 04 expressions. PDF 05-level modeling. PDF 06 user-defined primitives. P DF 07 data flow modeling. PDF 08 behavior modeling. PDF 09 modeling structure. PDF 10 other topics . PDF 11 certification. PDF 12 model. PDF 13 syntax reference. PDF
Platform: | Size: 4837376 | Author: 高 | Hits:

[Other] ActivH71sp1pch_1156042493

Description: ActivH71sp1pch有关active HDL得.好像.-ActivH71sp1pch HDL in the active. Like.
Platform: | Size: 33792 | Author: blanky | Hits:

[VHDL-FPGA-Verilog] VerilogHDLjihe

Description: 王金明的Verilog HDL程序集合，包含各个常用的程序-guo Verilog HDL procedures set includes all commonly used procedures
Platform: | Size: 113664 | Author: weishenghe | Hits:

[VHDL-FPGA-Verilog] 9.3_Pulse_Counter

Description: 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 　　9.3.1 脉冲计数器的工作原理 　　9.3.2 计数模块的设计与实现 　　9.3.3 parameter的使用方法 　　9.3.4 repeat循环语句的使用方法 　　9.3.5 系统函数$random的使用方法 　　9.3.6 脉冲计数器的Verilog-HDL描述 　　9.3.7 特定脉冲序列的发生 　　9.3.8 脉冲计数器的硬件实现 -based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] 9.6_PULSE_Level

Description: 基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时间的测量与显示 　　9.6.1 脉冲高电平和低电平持续时间测量的工作原理 　　9.6.2 高低电平持续时间测量模块的设计与实现 　　9.6.3 改进型高低电平持续时间测量模块的设计与实现 　　9.6.4 begin声明语句的使用方法 　　9.6.5 initial语句和always语句的使用方法 　　9.6.6 时标信号发生模块的设计与实现 　　9.6.7 脉冲高低电平持续时间测量的Verilog-HDL描述 　　9.6.8 脉冲高低电平持续时间测量的硬件实现 -Verilog-HDL-based hardware circuits to achieve 9.6 high and low pulse duration measurement and 9.6.1 show the high and low pulse duration of the working principle of measuring the high-low 9.6.2 duration measurement module 9.6.3 Design and Implementation of Improved Measurement of the high-low duration of the Design and Implementation of Module 9.6.4 begin the use of declaration statements 9.6.5 initial statement and statements always use 9.6.6 beacon signal occurs when the module design and 9.6.7 to achieve the high-low pulse duration measurement of Verilog-HDL description 9.6.8 high-low pulse duration measurement hardware implementation
Platform: | Size: 5120 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] 9.8_DISP256_GUO

Description: 基于Verilog-HDL的硬件电路的实现 9.8 基于256点阵的汉字显示 　　9.8.1 单个静止汉字显示的设计原理及其仿真实现 　　9.8.2 单个静止汉字显示的硬件实现 　　9.8.3 多个静止汉字显示的设计原理及其硬件实现 　　9.8.4 单个运动汉字显示的设计原理及其硬件实现 　　9.8.5 多个运动汉字显示的设计原理及其硬件实现 -based on Verilog-HDL hardware Circuit of 9.8 based on the lattice of 256 Chinese character display 9.8.1 static single Chinese character display and the design principle Simulation 9.8.2 single Chinese character was geostationary said the number of hardware 9.8.3 static display Chinese characters and hardware design principle to achieve single-9.8.4- Movement of the Chinese character display and hardware design principle to achieve a number of campaigns 9.8.5 Chinese character display and the design principle Hardware Implementation
Platform: | Size: 1024 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] cache

Description: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Platform: | Size: 4096 | Author: MingCheng | Hits:

[VHDL-FPGA-Verilog] LAC_adder16

Description: 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
Platform: | Size: 214016 | Author: Li Yanwei | Hits:

[VHDL-FPGA-Verilog] DES-source-code-by-HDL

Description: HDL实现的DES算法，及相关的Test bench激励文件-HDL achieve the DES algorithm, and the related documents incentive Test bench
Platform: | Size: 27648 | Author: zyx | Hits:

[ARM-PowerPC-ColdFire-MIPS] leg_source

Description: verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
Platform: | Size: 656384 | Author: lumingzhi | Hits:

[VHDL-FPGA-Verilog] shejiVerilogExample

Description: Verilog 程序例子 王金明：《Verilog HDL程序设计教程》程序例子，带说明。 -Verilog procedures guo examples : "Verilog HDL Design Guide" procedures example, take note.
Platform: | Size: 160768 | Author: mingming | Hits:

[Crack Hack] mini_aes

Description: aes算法的verilog hdl实现，供给大家作为参考 。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
Platform: | Size: 240640 | Author: 杨忠宇 | Hits:

[VHDL-FPGA-Verilog] NumClock

Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
Platform: | Size: 23552 | Author: 田世坤 | Hits:
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