Search - HDL - CodeBus

[VHDL-FPGA-Verilog] scu_all_fpga

Description: 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
Platform: | Size: 3072 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] keyboard_ps2_verilog

Description: 键盘鼠标的原代码,用FPGA实现,使用Verilog HDL编写,已经使用FPGA验正过了,完全可以用-keyboard and mouse of the original code, using FPGA, using Verilog HDL preparation, already in use FPGA-mortem is over, it can be used
Platform: | Size: 1480704 | Author: wpb3dm | Hits:

[Books] Verilog_HDL_Hardware_Description_Language

Description: 正式出版物《Verilog HDL 硬件描述语言》一书的精美 PDF 电子版。-official publications "Verilog HDL Hardware Description Language," a book of exquisite electronic PDF version.
Platform: | Size: 4767744 | Author: bigheadmonk | Hits:

[VHDL-FPGA-Verilog] hdl_coding_style

Description: HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.
Platform: | Size: 24576 | Author: 张丰 | Hits:

[Other] verilog_vga

Description: 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
Platform: | Size: 179200 | Author: yhr | Hits:

[Other] verilog_lcd

Description: 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Platform: | Size: 423936 | Author: yhr | Hits:

[Other] uartvhrilog

Description: This Verilog HDL description implements a UART.
Platform: | Size: 3072 | Author: chenhe | Hits:

[VHDL-FPGA-Verilog] Cpu_model

Description: Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
Platform: | Size: 1024 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[Other Embeded program] countqi

Description: 计数器同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
Platform: | Size: 271360 | Author: 周颖 | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212992 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章数字信号处理、计算、程序、算法和硬线逻辑的基本概念第二章 Verilog HDL设计方法概述第三章 Verilog HDL的基本语法第四章不同抽象级别的Verilog HDL模型第五章基本运算逻辑和它们的Verilog HDL模型第六章运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] news5f

Description: Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
Platform: | Size: 44032 | Author: 曹光明 | Hits:

[VHDL-FPGA-Verilog] SPtransform

Description: Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
Platform: | Size: 1024 | Author: 曹光明 | Hits:

[Books] DSP_WITH_FPGA

Description: The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification. -The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
Platform: | Size: 9935872 | Author: Jawen | Hits:

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