Description: Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
- [news5f] - Verilog HDL prepared by the five-frequen
- [SENANDCO] - participate in a contest (my part), incl
- [IIS2BT656] - this program will function as audio data
- [fifo_datapath] - verilog achieved, and through serial swi
- [verilogzzhwfy] - QPSK with Verilog realize the difference
- [FIFO_v] - FIFO verilog achieve, enclosing testbenc
- [mutiple] - Of PCM-encoded multiplexing and demultip
- [readme_vhd] - SERDES VHDL source code, you can achieve
- [serial_in] - Verilog serial signal to parallel signal
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