fifo_datapath verilog achieved, and through serial

Title: fifo_datapath

Category:
Embeded-SCM Develop
Tags:
[VHDL] [源码]
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2.37kb
Update:
2008-10-13
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Description: verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send

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To Search: VERILOG fifo verilog Verilog FIFO fifo verilog FIFO fifo_datapath

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