- Category:
- VHDL-FPGA-Verilog
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- 1.78kb
- Update:
- 2008-10-13
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Description: prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock
- [399] - VHDL prepared by the eight All-Canadian,
- [lcdexample] - cpld achieve parallel with the LCD scree
- [FPGA-1553B] - MIL-STD 1 1553B is a centralized control
- [PS2] - Xilinx sparten3E the keyboard and the de
- [serial] - Serial port data transmission experiment
- [readme_vhd] - SERDES VHDL source code, you can achieve
- [fd32_c] - latch，32bits.
- [auk_sdsdi] - for FPGA design ,written by Verilog HDL
- [FPGA_common_idea] - This article discusses the four commonly
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