Description: Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
- [uart_verilog] - include UART port of VERILOG source, the
- [ uart from opencores] - VHDL implement serial port, it can commu
- [51baudrate] - 51 baud rate calculation aids, can choos
- [UART] - UART serial procedures, verilog statemen
- [DS2438] - This is the introduction chapter of the
- [uart] - An FPGA using Verilog realization of the
- [fifo-1117] - This is the asynchronous FIFO realize th
- [RS232] - VHDL based on the RS232 communication pr
File list (Check if you may need any files):
Download