Search - divider

[Other resource] 16_16DIV

Description: 多位数除法程序，满足在单片机编程中对除法程序的需要，解决了单片机指令无除法程序的缺点，而且本程序不限制位数。-over the median divider, which meets in MCU Programming division procedures to the needs of SCM solutions division procedures directive without shortcomings, but the procedure does not limit the median.
Platform: | Size: 4771 | Author: 方丹 | Hits:

[Internet-Network] subr

Description: VHDL 8位无符号除法器试验报告计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。其实现方法是，将除法器分为两个状态：等待状态与运算状态。开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Platform: | Size: 83109 | Author: aa | Hits:

[Other resource] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45195 | Author: 刘建 | Hits:

[Other] fpdiv_vhdl四位除法器

Description: fpdiv_vhdl四位除法器 -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high
Platform: | Size: 983 | Author: 张洪 | Hits:

[LabView] Design-of-divider

Description: 除法器设计在FPGA板上的应用除法器设计在FPGA板上的应用-The application of FPGA in design of divider class.
Platform: | Size: 2048 | Author: 高浚玮 | Hits:

[Other] greatest-common-divider

Description: 一个用于计算两个数的最大公约数的逻辑算术单元-an arithmetic logic unit which is used to calculate the greatest common divider of two numbers
Platform: | Size: 3956736 | Author: zhangyu | Hits:

[Other] divider

Description: 用Verilog实现的除法器，通过了编译和测试，可以放心使用。-Divider implemented using Verilog, by compiling and testing, you can rest assured that use.
Platform: | Size: 129024 | Author: 彭 | Hits:

[Other] divider

Description: 输出任意频率的分频器，使用verilog语言实现-The divider wright using verilog
Platform: | Size: 462848 | Author: 宋辉 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 分频器。可实现任意整数分频。占空比为50％，带复位端。-Frequency divider Arbitrary integer frequency can be achieved. Duty cycle is 50 , with reset terminal.
Platform: | Size: 338944 | Author: xdh | Hits:

[VHDL-FPGA-Verilog] Frequency-divider

Description: 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
Platform: | Size: 10240 | Author: 陆晓忆 | Hits:

[VHDL-FPGA-Verilog] NC-divider-design

Description: 1、学习数控分频器的设计、分析和测试方法。 2、了解和掌握分频电路实现的方法。 3、掌握EDA技术的层次化设计方法。 -NC divider design
Platform: | Size: 88064 | Author: 漆广文 | Hits:

[Other] design-of-divider-

Description: 应用FPGA软件编写的关于除法器的小程序，适合初学者学习，很实用，而且很简单，-FPGA application software prepared by the divider small program for beginners to learn, very practical and very simple, Ha ha ha
Platform: | Size: 2048 | Author: 李宁 | Hits:

[Other] divider

Description: a vhdl code for divide operation in fpga spartan6
Platform: | Size: 1408000 | Author: ghanbari1995 | Hits:

[LabView] 7P(divisionymulti)

Description: divider and multiplier number labview
Platform: | Size: 5120 | Author: angel134 | Hits:

[OS program] Divider

Description: 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
Platform: | Size: 103424 | Author: wmy36 | Hits:

[Other] Divider

Description: this is divider for verilog
Platform: | Size: 5120 | Author: Hainder | Hits:

[VHDL-FPGA-Verilog] frequency divider and testbench

Description: a frequency divider and test bench with simulation results
Platform: | Size: 493568 | Author: abitofhero | Hits:

[Other] RPWM-matlab

Description: clock divider program by using VHDL
Platform: | Size: 869376 | Author: muthukumarvlsi | Hits:

[VHDL-FPGA-Verilog] clock divider example

Description: this is clock divider example code
Platform: | Size: 755 | Author: prabhu | Hits:

[VHDL-FPGA-Verilog] Divider-vhdl

Description: Divider-VHDL by spartan 6
Platform: | Size: 16131 | Author: dornabit | Hits:

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[Other resource] 16_16DIV

[Internet-Network] subr

[Other resource] 数字系统设计相关

[Other] fpdiv_vhdl四位除法器

[LabView] Design-of-divider

[Other] greatest-common-divider

[Other] divider

[Other] divider

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] Frequency-divider

[VHDL-FPGA-Verilog] NC-divider-design

[Other] design-of-divider-

[Other] divider

[LabView] 7P(divisionymulti)

[OS program] Divider

[Other] Divider

[VHDL-FPGA-Verilog] frequency divider and testbench

[Other] RPWM-matlab

[VHDL-FPGA-Verilog] clock divider example

[VHDL-FPGA-Verilog] Divider-vhdl

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