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[Software Engineering] zhen1

Description: 本文设计的数字分接器是由帧同步提取模块、位同步提取模块、帧同步移位和时序信号恢复模块、分路器模块、串/并转换电路模块五部分组成-Digital tapping machine is designed in this paper by the frame synchronization extraction module, a synchronous extraction module, the displacement of frame synchronization and timing signal recovery module, divider module, string/and conversion circuit module of five parts
Platform: | Size: 524288 | Author: 訚鹏 | Hits:

[Other] firstTry

Description: pscad简单分压模型。包含电压表和电流表，实时显示波形-pscad simple voltage divider models. Includes voltmeter and ammeter, real-time waveform display
Platform: | Size: 1024 | Author: 杨光 | Hits:

[VHDL-FPGA-Verilog] divby4.5.v

Description: This Divider by 4.5.-This is Divider by 4.5.
Platform: | Size: 1024 | Author: Gourav Agarwal | Hits:

[VHDL-FPGA-Verilog] divby3.v

Description: This Divider by 3.-This is Divider by 3.
Platform: | Size: 1024 | Author: Gourav Agarwal | Hits:

[Linux-Unix] rv740_dpm

Description: rv740 get decoded reference divider for Linux v2.13.6.
Platform: | Size: 3072 | Author: tiuxouzan | Hits:

[Linux-Unix] clk-fixed-factor

Description: basic fixed multiplier and divider clock that cannot gate.
Platform: | Size: 1024 | Author: jdfzws | Hits:

[Linux-Unix] clk-imx6q

Description: The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. -The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
Platform: | Size: 6144 | Author: terneng998 | Hits:

[Other] Binary_Divider_VHDL.txt.tar

Description: Code for a binary divider state machine.
Platform: | Size: 1024 | Author: moverx | Hits:

[VHDL-FPGA-Verilog] divizor_fregventa

Description: contains a divider on the frequency that can be obtained at 13.5 MHz output if the input signal is applied to a 40 MHz
Platform: | Size: 1021952 | Author: Mo11 | Hits:

[Other] DivFrec

Description: Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
Platform: | Size: 2048 | Author: Mario | Hits:

[JSP/Java] jquerybeforeafter

Description: jquery与HTML5实现拖动图片变换效果，拖动中间的分隔线，可看到两种截然不同的效果，一边是清淅的图像，一边是模糊的图片，当然是调用了两张分别处理过的图片，综合运用jquery.beforeafter-1.3.js，jquery-ui-1.8.13.custom.min.js，jquery-1.6.1.min.js等jquery插件来实现，在图片中你可看到模特的脸，左边是不清淅的，右边则是高清的，你可通过中间的分隔条来向左或向右拖动查看。 　　因为用了HTML5技术，所以测试时候IE8无效果，请使用火狐或Opera、Chrome等网页浏览器。-jquery and HTML5 drag the picture transformed to achieve the effect, drag the divider in the middle, you can see two very different effect, while the image is clear mission, while the blurred picture, of course, is to call the two were treated pictures, integrated use jquery.beforeafter-1.3.js, jquery-ui-1.8.13.custom.min.js, jquery-1.6.1.min.js and other jquery plugins to achieve, in the picture you can see the model s face, the left is not clear mission, the right is the high-definition, you can drag the view to the left or right through the middle of the divider. Because use of the HTML5 technology, so the test when IE8 no results, use Firefox or Opera, Chrome and other web browsers.
Platform: | Size: 274432 | Author: npudn9 | Hits:

[Linux-Unix] clk-ls1x

Description: imx integer fixup divider clock for Linux v2.13.6.
Platform: | Size: 2048 | Author: ginkengvv | Hits:

[Linux-Unix] irq_nmi_defs_asm

Description: mxs fractional divider clock for Linux v2.13.6.
Platform: | Size: 2048 | Author: nunnazn | Hits:

[Linux-Unix] clkt34xx_dpll3m2

Description: OMAP34xx M2 divider clock code.
Platform: | Size: 1024 | Author: rangfieben | Hits:

[VHDL-FPGA-Verilog] traffic_light_3_09

Description: 数码管驱动、HC595驱动、VHDL、分频器-Digital tube drive, HC595 drive, VHDL, divider
Platform: | Size: 1497088 | Author: 曾经 | Hits:

[VHDL-FPGA-Verilog] myproj

Description: 1) 可以产生四种波形：正弦波，方波，三角波，锯齿波。 2) 实现分频可调，分频比从2~256可调，通过两个按键进行+1和-1的调整。 3) 信号幅度可调，幅度增益从1~4倍可调，过两个按键进行+1和-1的调整。 4) 8位数码管的前3位显示分频比，最后一位显示幅度增益，中间的四位分别代表四种波形是否输出，若输出则显示’1’,否则显示’0’。 5) 可实现四种波形的叠加，当有两种波形叠加时，增益不能超过3，当是四种或三种波形叠加时，增益只能为1. -1) can produce four waveforms: sine, square, triangle wave, sawtooth wave. 2) to achieve an adjustable divider, the division ratio is adjustable 2 to 256, by adjusting the two keys is set to+1 and-1. 3) the adjustable signal amplitude, the amplitude of the gain is adjustable 1 to 4 times, after adjustment of the two keys is set to+1 and-1. Before 3 4) 8 digital tube display divider ratio, the last one is displayed amplitude gain, in the middle of the four represent the four waveform is output, if the output is displayed to 1 , otherwise the 0 . 5) Four superimposed waveforms can be achieved when there are two superimposed waveforms, the gain can not be more than three, four, or three waveforms when it is superimposed, the gain can only be one.
Platform: | Size: 171008 | Author: 陈伟豪 | Hits:

[VHDL-FPGA-Verilog] fp_prj

Description: 分频器，Verilog语音编写，quartus仿真过，可以利用使蜂鸣器发生-Frequency divider, Verilog speech writing, quartus simulation, can make use of the buzzer
Platform: | Size: 204800 | Author: 孟稳 | Hits:

[VHDL-FPGA-Verilog] Lab1~3

Description: 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
Platform: | Size: 2226176 | Author: | Hits:

[VHDL-FPGA-Verilog] cymometer

Description: 硬件频率计的实现，包括十分频，门控信号产生，频率测量等-cymometer implementation， involving 10 times divider, generating gate controling signal and frequency measurement
Platform: | Size: 2048 | Author: s | Hits:

[VHDL-FPGA-Verilog] second

Description: 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BCD/7 segment decoder IC 74LS47 simulation, single-tube type stable operating point voltage divider bias circuit simulation and 8 quiz Responder circuit design
Platform: | Size: 465920 | Author: 文闯 | Hits:
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