Search - divider

[MPI] arban

Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: | Size: 1024 | Author: arban | Hits:

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 241664 | Author: 赵惠 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
Platform: | Size: 35840 | Author: digua | Hits:

[Software Engineering] cpupipeline

Description: CPU设计，加法器，乘法器，除法器等，有原理讲解等。挺不错的资料-CPU design, adders, multiplier, divider and so on and so have the principle. Very good information
Platform: | Size: 1864704 | Author: 李佳 | Hits:

[Software Engineering] 353fpga

Description: 用vhdl实现的除法器-Achieved using VHDL divider
Platform: | Size: 1024 | Author: wenhao sun | Hits:

[Other] altclklock

Description: 如何给时钟倍频或者分频，以及altera提供的IP核使用方法-How to clock multiplier or divider, as well as to provide the IP of nuclear altera use
Platform: | Size: 2048 | Author: 杨华 | Hits:

[RFID] dpll

Description: DPLL由鉴相器模K加减计数器脉冲加减电路同步建立侦察电路模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍) 为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器被除数和除数均为16位整数，16位小数商为32位整数，16位小数余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[Other] testbench

Description: 32位除法器的测试程序，由随机向量产生函数产生一组随机数来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
Platform: | Size: 5120 | Author: 李春阳 | Hits:

[Embeded-SCM Develop] yifabandaoti

Description: 时钟分频电路实现精讲(19 pages)——意法半导体-Clock divider circuit精讲(19 pages)- STMicroelectronics
Platform: | Size: 90112 | Author: 悠酷男孩 | Hits:

[VHDL-FPGA-Verilog] dividers.tar

Description: 无符号类型的除法器,有VHDL语言描述了无符号的除法器,包括测试文件-Unsigned type of divider, a VHDL language description of the divider unsigned, including the test file
Platform: | Size: 5120 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] div_js

Description: 技术分频器。把时钟分为奇数个，好像我做出来是个通用的。-Technology divider. The clock is divided into odd-numbered months, as I make out is a common.
Platform: | Size: 272384 | Author: catalina | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[Windows Develop] clock-divider

Description: 这是一个关于时钟分频率器的程序，它可以实现频率的扩大。-This is a device on the clock frequency of the procedure, it can realize the expansion of the frequency.
Platform: | Size: 1024 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3072 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] te187

Description: 基于高速串行BCD 码除法的数字频率计的设计-Based on high-speed serial BCD code of the digital frequency divider Design
Platform: | Size: 208896 | Author: 张贺寅 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[Software Engineering] pll_component_design_matlab

Description: PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code-PLL system LPF/PFD/VCO/Divider model in Matlab, the Matlab will PLL system model of each module, the easy analysis of the whole PLL loop stability characteristics, lock time ... ... the appendix contains a complete Matlab code
Platform: | Size: 92160 | Author: xin | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

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