Search - divider

[VHDL-FPGA-Verilog] div_n

Description: verilog占空比50奇偶任意奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
Platform: | Size: 1024 | Author: 龚俊杰 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 用VERILOG实现一个被除数为8位、除数为4位的高效除法器-With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] Fredevider_n

Description: 任意N偶数倍频率分频器VHDL语言，编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
Platform: | Size: 24576 | Author: 黑雾 | Hits:

[Software Engineering] A-Universal-Programmable-Dual-Divider

Description: 一种通用的可编程双模分频器A Universal Programmable Dual Divider-A Universal Programmable Dual Divider
Platform: | Size: 569344 | Author: bing02020 | Hits:

[VHDL-FPGA-Verilog] time-divider

Description: 时钟分频器，这个虽然简单一点，但还是觉得很不错的，-Clock divider, this is simple point, but still felt very good,
Platform: | Size: 2048 | Author: 木三清 | Hits:

Description: 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
Platform: | Size: 10240 | Author: 小杰 | Hits:

[Software Engineering] Sequential-Divider

Description: Partial design of a sequential divider using GATES
Platform: | Size: 457728 | Author: kigz | Hits:

[Software Engineering] Fixpoint-Divider

Description: 定点除法器的设计,关于定点除法器的原理，和设计，以及电路设计-Fixpoint Divider Design
Platform: | Size: 32768 | Author: yanlin | Hits:

[VHDL-FPGA-Verilog] divider

Description: FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
Platform: | Size: 1024 | Author: 余木 | Hits:

[Algorithm] divider

Description: 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
Platform: | Size: 1024 | Author: liuyi | Hits:

[VHDL-FPGA-Verilog] frequency-divider

Description: anything frequency divider-frequency divider
Platform: | Size: 1024 | Author: wudongdong | Hits:

[VHDL-FPGA-Verilog] VHDL-test-code-divider

Description: VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Platform: | Size: 1024 | Author: zpatel | Hits:

[VHDL-FPGA-Verilog] verilog-divider-code

Description: Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
Platform: | Size: 2048 | Author: duwenjian | Hits:

[File Operate] File-Divider-vb

Description: 文件分割机，是一个很好的工具，是学习的好源码。-File Divider is a good tool, is a good source for learning.
Platform: | Size: 26624 | Author: 海神 | Hits:

[VHDL-FPGA-Verilog] The-use-of-VHDL-divider-design

Description: 分频器的各种设计方法，及源代码，源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The use of VHDL divider design
Platform: | Size: 5120 | Author: 王子冉 | Hits:

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

Description: 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的分频器。本次设计实现了包括整数、半整数和小数这三种不同类型分频器的分频，在设计过程中，系统主芯片采用EP1C6Q240C8，各个模块在QuartusⅡ上进行编程调试和仿真通过后，在GW48-SOPC上进行了下载。通过对各个部分测试后表明均能正确分频，完成了对系统的软件和硬件的设计，达到了系统的设计要求。 -Frequency divider refers to the frequency of the output signal as the input signal 1/N of electronic circuits. N is the frequency coefficient. In many electronic equipments such as the electronic clock, frequency synthesizers, which need different frequency signals work together and common way is to use the stability of the crystal oscillator as vibration source by converting the frequency components all needed. The frequency divider is a major means of conversion. In this paper, with the analytic study and review of trend basis of the technical frequency, a functional, reliable, economic and other design principles as the goal, this paper introduces a number of points frequency of the design and implementation based on FPGA. This design adopts the technology of EDA and hardware description language VHDL as logical description means of designing files. Under the environment of QuartusⅡ tools and the top-to-down approach, they build jointly a frequency divider by the basic modules base
Platform: | Size: 5120 | Author: 吴红梅 | Hits:

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[VHDL-FPGA-Verilog] div_n

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] Fredevider_n

[Software Engineering] A-Universal-Programmable-Dual-Divider

[VHDL-FPGA-Verilog] time-divider

[VHDL-FPGA-Verilog] diwu

[Software Engineering] Sequential-Divider

[Software Engineering] Fixpoint-Divider

[VHDL-FPGA-Verilog] divider

[Algorithm] divider

[VHDL-FPGA-Verilog] frequency-divider

[VHDL-FPGA-Verilog] VHDL-test-code-divider

[VHDL-FPGA-Verilog] clock-divider

[VHDL-FPGA-Verilog] verilog-divider-code

[File Operate] File-Divider-vb

[VHDL-FPGA-Verilog] The-use-of-VHDL-divider-design

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

[VHDL-FPGA-Verilog] divider

[Delphi VCL] Divider

[VHDL-FPGA-Verilog] divider

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