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[source in ebook] ref

Description: non-storing divider in verilog code
Platform: | Size: 1024 | Author: leo | Hits:

[VHDL-FPGA-Verilog] HG_chufaqi_clajiafaqi

Description: VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
Platform: | Size: 2048 | Author: Huanggeng | Hits:

[VHDL-FPGA-Verilog] f_divider

Description: 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
Platform: | Size: 455680 | Author: abu_faisul | Hits:

[MPI] divider

Description: 几个有用的分频器电路的VHDL实现。有需要的进来-The divider using VHDL code. if you want, please come in. welcome to give some suggestion. Thank you.
Platform: | Size: 1024 | Author: pengdasong | Hits:

[Other] FF_Divider_ISCAS04

Description: A Novel Ultra High Speed Flip Flop Base Frequency Divider
Platform: | Size: 154624 | Author: bamadude | Hits:

[Other] Freq_Divider

Description: frequency divider using verilog
Platform: | Size: 1024 | Author: hazwaj | Hits:

[VHDL-FPGA-Verilog] Divider-design-in-three-ways

Description: 三种方式设计的分频器（常用于产生秒脉冲）-Divider design in three ways (often used to produce second pulse)
Platform: | Size: 2048 | Author: luo | Hits:

[Other] divider_latest.tar

Description: floating point divider
Platform: | Size: 5120 | Author: charanyakannan | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[Software Engineering] divider

Description: divider code .. in VHDL language
Platform: | Size: 180224 | Author: Daaalal | Hits:

[ARM-PowerPC-ColdFire-MIPS] 5956447divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
Platform: | Size: 3072 | Author: wfwef | Hits:

[Mathimatics-Numerical algorithms] divider

Description: 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
Platform: | Size: 1024 | Author: liu | Hits:

[VHDL-FPGA-Verilog] divider

Description: 高效率的VERIFLOG描述语言的除法器,比一般的速度高-Efficient VERIFLOG description language of the divider, than the average high speed
Platform: | Size: 142336 | Author: henry | Hits:

[Com Port] 9600divider

Description: 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
Platform: | Size: 195584 | Author: liujieyu | Hits:

[VHDL-FPGA-Verilog] divider

Description:
Platform: | Size: 322560 | Author: Grazy-Wolf~.~ | Hits:

[VHDL-FPGA-Verilog] divider

Description: 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
Platform: | Size: 96256 | Author: 李丽萍 | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] divider

Description: 介绍了verilog设计中一种分频器的写法，很通用实惠，方便移植-Introduced the verilog design the wording of a kind of divider, a very common benefit, to facilitate migration
Platform: | Size: 1024 | Author: lifejoy | Hits:

[VHDL-FPGA-Verilog] divider

Description: 由VHDL撰写的强大多功能除频器，只需由上方参数载入除频数N及N的宽度(2的次方)即可使用。 可以除以任意整数，包含奇数。-Written by the powerful multi-functional VHDL divider, just above the parameters included in addition to the frequency width of N, N-(2 power) can be used. Can be divided by any integer, including odd.
Platform: | Size: 288768 | Author: Risger | Hits:
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