Search - divider

[VHDL-FPGA-Verilog] divider

Description: 分频器，可以实现简单的分频功能,适合初学VHDL语言的初学者-divider , it can realize simple divier
Platform: | Size: 1024 | Author: qinjuchao | Hits:

[SCM] divider-procedures

Description: 使用PROTELUS，对ATMEGA16编写的分频器程序并仿真-Use PROTELUS ATMEGA16 written divider procedures and simulation
Platform: | Size: 38912 | Author: 浩哥 | Hits:

[VHDL-FPGA-Verilog] Divider

Description: 一个除法器的FPGA代码设计 Divider-fpga Divider
Platform: | Size: 2048 | Author: 林伟 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 分频器，可任意选择参数分频，带有完整的测试程序-Divider, optional parameters divider with a complete test program
Platform: | Size: 1024 | Author: xiangzi | Hits:

[MiddleWare] Simplified-2-frequency-divider

Description: 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.
Platform: | Size: 3072 | Author: zhangjinbao | Hits:

[VHDL-FPGA-Verilog] divider

Description: VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
Platform: | Size: 1024 | Author: Solomon | Hits:

[Software Engineering] signal-phase-voltage-divider

Description: 电力系统仿真软件测试（PSCAD、EMTDC），希望对初学者有用-signal phase voltage divider
Platform: | Size: 19456 | Author: 黑鬼 | Hits:

[VHDL-FPGA-Verilog] The-key-control-divider

Description: 这是一个利用VHDL代码编写通过按键控制的分频器，通过给按键s3、s2、s1、s0赋不同的值，可以使分频器输出不同频率，此代码原用于自制示波器的分频。-This is a use of the VHDL code written by key control divider divider output through to key s3, s2, s1, s0 endowed different values, different frequencies, this code is the original for homemade oscilloscope divider.
Platform: | Size: 6144 | Author: yubaoming | Hits:

[ARM-PowerPC-ColdFire-MIPS] divider

Description: divider 这个程序是教你如何写一个偶数的分频器，用它可以完成任意进制偶数分频器-divider of this program is to teach you how to write an even divider, you can use it to complete any hex even-numbered divider
Platform: | Size: 1024 | Author: nx74110 | Hits:

[Other Embeded program] Frequency-divider

Description: 本例程为简易分频器。实验前，请用排线（杜邦线）将TX-1C学习板的P1^0管脚与P3^2(INT0)管脚相连。因为P1^0用来模拟外界波形输入，它提供周期为100ms的方波，与T1管脚相连后，T1可对其进行周期计数。程序中的变量pp决定着分频系数，其值乘以2即为分频系数。改变其值可以得到相应的分频输出波形（方波）。P1^1为输出管脚，将其连接示波器可以看到分频后的波形。-This routine for simple frequency divider. Before experiment, please use platoon line (dupont line) will TX- 1 c ^ 0 learning plate P1 of the pin and P3 ^ 2 (INT0) pin connected. Because P1 ^ 0 used to simulate the outside world wave input, it provides cycle for 100 ms square wave, and T1 pin connected, T1 can carry on the cycle count. The procedure in the variable pp determines the scale coefficient, the value multiplied by 2 is the crossover factor. To change its value can get corresponding crossover output waveform (square). P1 ^ 1 as output pin, its connection oscillograph can see points after the frequency of the wave.
Platform: | Size: 22528 | Author: zhanghuasheng | Hits:

[Other] frequency-divider-graphic-design

Description: 数字系统EDA 多级分频器图形设计熟悉和掌握MAX+PlusⅡ的编译、仿真操作。-The multi-level divider graphic design of digital systems EDA familiar with and master MAX+Plus Ⅱ compilation, simulation operation.
Platform: | Size: 256000 | Author: 王海阔 | Hits:

[Other] FPGAfrequency-divider

Description: 一种基于FPGA的分频器实现，讲的很详细，很实用，希望能帮助您。-A kind of the frequency divider based on FPGA realization, speak very detailed, very practical, the hope can help you.
Platform: | Size: 61440 | Author: 陈吧 | Hits:

[VHDL-FPGA-Verilog] simple-divider

Description: simple divider vhdl code
Platform: | Size: 1024 | Author: kavi | Hits:

[VHDL-FPGA-Verilog] VHDL-divider-design

Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
Platform: | Size: 320512 | Author: 黄玲 | Hits:

[VHDL-FPGA-Verilog] Divider

Description: 除法的fpga实现开发环境ise 语言vhdl-divider ise vhdl fpga
Platform: | Size: 4413440 | Author: 孙范瑞 | Hits:

[Other] Three-divider

Description: 用verilog硬件描述语言实现的三分频器-Three divider
Platform: | Size: 25600 | Author: 丁凤 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 除法器，经过验证,性能优良，值得下载，应该是定点除法的-divider,it is verified and good performance
Platform: | Size: 6144 | Author: 陈毅 | Hits:

[VHDL-FPGA-Verilog] divider

Description: Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
Platform: | Size: 1024 | Author: zhuojun chen | Hits:

[Other] divider

Description: verilog的除法器有多重方法很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
Platform: | Size: 1097728 | Author: ran | Hits:

[VHDL-FPGA-Verilog] The-FPGA--fractional-divider

Description: The FPGA-based realization of the fractional divider
Platform: | Size: 269312 | Author: 马俊汉 | Hits:

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[VHDL-FPGA-Verilog] divider

[SCM] divider-procedures

[VHDL-FPGA-Verilog] Divider

[VHDL-FPGA-Verilog] divider

[MiddleWare] Simplified-2-frequency-divider

[VHDL-FPGA-Verilog] divider

[Software Engineering] signal-phase-voltage-divider

[VHDL-FPGA-Verilog] The-key-control-divider

[ARM-PowerPC-ColdFire-MIPS] divider

[Other Embeded program] Frequency-divider

[Other] frequency-divider-graphic-design

[Other] FPGAfrequency-divider

[VHDL-FPGA-Verilog] simple-divider

[VHDL-FPGA-Verilog] VHDL-divider-design

[VHDL-FPGA-Verilog] Divider

[Other] Three-divider

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] divider

[Other] divider

[VHDL-FPGA-Verilog] The-FPGA--fractional-divider

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