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[Software Engineering] ddr_sdr_V1_1

Description: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
Platform: | Size: 37888 | Author: james | Hits:

[VHDL-FPGA-Verilog] sdram_controller_latest.tar

Description: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Platform: | Size: 30720 | Author: Andrei | Hits:

[SCM] S3C6410_core_sch

Description: ok6410最新核心板最小系统原理图，包含mobile ddr， nandflash-ok6410 latest minimum system schematic core board, including mobile ddr, nandflash
Platform: | Size: 128000 | Author: jerry | Hits:

[Other Embeded program] Hardware_and_Layout_Design_Considerations_for_DDR_

Description: DDR SDRAM接口的硬件和布线设计指南。DDR SDRAM的传输速度越来越高，对走线的要求也越来越高。-DDR SDRAM HARDWARE LAYOUT DESIGN
Platform: | Size: 692224 | Author: 朱伟华 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_design_and_conclusion

Description: DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
Platform: | Size: 338944 | Author: 李中梅 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Platform: | Size: 8483840 | Author: 熊熊 | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMconclude

Description: DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some reference
Platform: | Size: 2262016 | Author: 董萌 | Hits:

[VHDL-FPGA-Verilog] XAPP200_ddr_sdram_64b

Description: Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
Platform: | Size: 1626112 | Author: jc | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_controller

Description: ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
Platform: | Size: 693248 | Author: | Hits:

[Other] ddr

Description: DDR solution for problem in NPC contest
Platform: | Size: 1024 | Author: GestureWorld | Hits:

[VHDL-FPGA-Verilog] ddr_100Mhz_2011.03.12

Description: 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.
Platform: | Size: 6132736 | Author: 张元甲 | Hits:

[Linux-Unix] DDR-failure-analysis

Description: DDR failure analysis
Platform: | Size: 800768 | Author: leego | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM

Description: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
Platform: | Size: 54272 | Author: syf | Hits:

[VHDL-FPGA-Verilog] DDR

Description: 关于DDR布线规范，用于指导PCB布线.-Wiring on the DDR specification, PCB layout for
Platform: | Size: 1957888 | Author: tl | Hits:

[VHDL-FPGA-Verilog] emb-dev-c3-appsel

Description: vhdl code for altera ddr design
Platform: | Size: 4072448 | Author: clement | Hits:

[VHDL-FPGA-Verilog] TEST-BENCH.vhd

Description: test bench for ddr 1
Platform: | Size: 2048 | Author: shiva | Hits:

[DSP program] tests

Description: 6437开发板测试程序,RAM,DDR,LED,RTC,USB,VIDEO,SPIROM-DM6437 DEMO program
Platform: | Size: 6777856 | Author: gemmy | Hits:

[VHDL-FPGA-Verilog] model

Description: 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
Platform: | Size: 7168 | Author: momowang | Hits:

[ARM-PowerPC-ColdFire-MIPS] DDR

Description: S3C6410 ARM11的DDR裸机驱动编程，使用RVDS2.2配置j-linkV8调试，启动方式是nandflash-S3C6410 ARM11 DDR bare-metal programming, using the RVDS2.2 configuration j-linkV8 commissioning, start-up mode is nandflash
Platform: | Size: 694272 | Author: duyb | Hits:
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