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[Software Engineering] S3C6410X_Type_Circuit_Design_Guide_rev1.00

Description: S3C6410 線路設計時一定要參考的文件,尤其是DDR Layout guide一定要看.以免開發出的板子不能動.-S3C6410 circuit design must read this documents, especially DDR Layout guide. To avoid your board can not run in high speed.
Platform: | Size: 2451456 | Author: 呂宜有 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode

Description: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Platform: | Size: 477184 | Author: fdasfds | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
Platform: | Size: 73728 | Author: sy | Hits:

[ARM-PowerPC-ColdFire-MIPS] OXE800SE_OXE800DSE

Description: SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM controller，PCI HOST。
Platform: | Size: 974848 | Author: gxliu | Hits:

[Communication-Mobile] DDR_interface

Description: 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see
Platform: | Size: 28672 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
Platform: | Size: 475136 | Author: 寒心雪林 | Hits:

[Software Engineering] TM4600-4100-AS1690_Sch_zl2(DDR)_3

Description: Quanta ZL2 motherboard schematic
Platform: | Size: 1286144 | Author: Dmitriy | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[VHDL-FPGA-Verilog] 512Mb_ddr_Modules

Description: DDR and DDR DIMM Controller
Platform: | Size: 23552 | Author: starplus | Hits:

[VHDL-FPGA-Verilog] 03.EDK8.2

Description: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Platform: | Size: 22821888 | Author: 肖姗姗 | Hits:

[Editor] DDRSDRAM

Description: DDR SDRAM设计及调试经验总结.pdf
Platform: | Size: 338944 | Author: arens09 | Hits:

[VHDL-FPGA-Verilog] sdram32

Description: DDR SDRAM source verilog source codes
Platform: | Size: 25600 | Author: sachin | Hits:

[OS Develop] ddr2_device_operation_timing_diagram_may_07_1

Description: DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
Platform: | Size: 1933312 | Author: yangjian | Hits:

[VHDL-FPGA-Verilog] DDRctroll

Description: ddr 的fpga 控制器的实现 仿真正确-ddr controller fpga to achieve the correct simulation
Platform: | Size: 3970048 | Author: gongranli | Hits:

[VHDL-FPGA-Verilog] SouceCode_0f_DDR_SDRAM_Controller_by_VHDL

Description: VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
Platform: | Size: 683008 | Author: SYQ | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
Platform: | Size: 13312 | Author: tom | Hits:

[Embeded Linux] nandboot

Description: mx27 bootloader nandboot cpu:i.mx27 nand:K9F2G08U0A ddr:HYB18M1G320BF-7[1][1].5
Platform: | Size: 94208 | Author: 任浩然 | Hits:

[DSP program] ddr

Description: 在TMS320DM6446 DSP环境下，对DDR2进行读写测试。-In the TMS320DM6446 DSP environment, reading and writing tests for DDR2.
Platform: | Size: 69632 | Author: 万传 | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:
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