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[Other] mem-ctrl-rtl

Description: 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
Platform: | Size: 44032 | Author: zz | Hits:

[Other Embeded program] ddr_sdram_controller

Description: DDR SDRAM Controller design
Platform: | Size: 2400256 | Author: Jerry | Hits:

[Embeded Linux] DS-0050_OXE800SE_datasheet

Description: SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM controller，PCI HOST。-The OXE800SE is a highly integrated, powerful network attached storage controller for bridging between Ethernet and SATA hard disks.
Platform: | Size: 317440 | Author: lzch | Hits:

[ARM-PowerPC-ColdFire-MIPS] HY5DU121622CFP

Description: 64MB 512Mb, 16bit, DDR SDRAM MEMORY
Platform: | Size: 1558528 | Author: lzch | Hits:

[Other] ddr-sdram-verilog-resource

Description: 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Platform: | Size: 896000 | Author: wangyuzhuo | Hits:

[Software Engineering] SDRAM

Description: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Platform: | Size: 1903616 | Author: luyi | Hits:

[Software Engineering] S5PC100_UM_REV1.04

Description: Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 166MHz memory clock. DDR, mobileDDR, DDR2 * in actually, i run c100 board ddr2 bus clock at 280MHz in WinCE 6.0
Platform: | Size: 12115968 | Author: john | Hits:

[Linux-Unix] ddr

Description: 测试DDR内存，Linux下编译运行-Test Demos under CCS\tests\ddr
Platform: | Size: 71680 | Author: jiangpeijian | Hits:

[VHDL-FPGA-Verilog] DDR_prj

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
Platform: | Size: 4781056 | Author: zhanghe | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_MT46V32M16TG

Description: ddr控制器 对DDR实现读写控制-ddr control
Platform: | Size: 548864 | Author: 张琦 | Hits:

[Software Engineering] DDRcontroller

Description: 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
Platform: | Size: 800768 | Author: 张琦 | Hits:

[Program doc] DDRdesigen.pdf

Description: DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
Platform: | Size: 338944 | Author: Mike | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAMDesignTutorials

Description: Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
Platform: | Size: 3154944 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] DDR

Description: HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Platform: | Size: 3968000 | Author: 网络蚂蚁 | Hits:

[Communication-Mobile] Magnetic

Description: 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰，还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号，像一些RF电路，PLL，振荡电路，含超高频存储器电路（DDR SDRAM，RAMBUS等）都需要在电源输入部分加磁珠，而电感是一种蓄能元件，用在LC振荡电路，中低频的滤波电路等，其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line frequency noise and interference peak, also has the ability to absorb the static pulse. Bead is used to absorb the high frequency signal, as some RF circuits, PLL, oscillator circuits, including ultra-high frequency memory circuit (DDR SDRAM, RAMBUS, etc.) need to increase the power input part of the bead, while the inductor is a store to components used in the LC oscillator circuit, the low-frequency filter circuit, the application frequency range rarely exceeds 50MHZ.
Platform: | Size: 5120 | Author: 范伟 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-verilog

Description: ddr_sdram开发参考verilog建模-ddr_sdram with verilog
Platform: | Size: 753664 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] ddr_code

Description: 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware description language
Platform: | Size: 11264 | Author: 阳阳 | Hits:

[DSP program] ddr

Description: DM6446 ddr ccs 仿真器测试程序-DM6446 ddr program in CCS
Platform: | Size: 69632 | Author: 鲍协浩 | Hits:

[VHDL-FPGA-Verilog] DX-PHY

Description: ddr phy design spec and example-ddr phy design spec and example!!
Platform: | Size: 250880 | Author: yangxf | Hits:

[DSP program] omap3530

Description: omap3530的datasheet，OMAP3530集成ARM+DSP+3D,ARM部分主频达到600MHZ，DSP采用430-MHz TMS320C64x+™ DSP Core，DDR可从128MB扩展到512M，尺寸基于7寸数字屏，主板由核心板和底板构成-omap3530 the datasheet, OMAP3530 integrates ARM+ DSP+3 D, ARM parts of speeds up to 600MHZ, DSP with 430-MHz TMS320C64x+ ™ DSP Core, DDR can be expanded from 128MB to 512M, size 7-inch digital screen on the motherboard from the core board and the floor constitute
Platform: | Size: 2698240 | Author: 林明 | Hits:
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