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Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip
(SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent
method for simulation and synthesis. The library is vendor independent, with support for different
CAD tools and target technologies. A unique plug&play method is used to configure and connect
the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
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Size: 103163 |
Author: 岳昆 |
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Description: DDR sdram 包含的完整的源码,仿真的相关文件
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Size: 1021984 |
Author: 飞翔 |
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Description: verilog hdl coding DDR sdram control for fpga
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Size: 27946 |
Author: 王郁 |
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Description: 开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测,串行通讯测试,以太网测试,DDR测试,QDR存储器测试,PCI总线检测等等。
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Size: 1758343 |
Author: saishindou |
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Description: ddr verilog代码,实现DDR内存控制,是一个高效率的程序
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Size: 39298 |
Author: liujun |
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Description: 关于DDR,DDR2,DDR3和MMC的标准规范。
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Size: 13941603 |
Author: 崔海群 |
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Description: 利用v4fpga实现sdram ddr控制器设计,很详细的,很实用的资料
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Size: 418207 |
Author: hesonwhb |
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Description: nois中基于c的ddr等存储器的checksum的实现.
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Size: 6699 |
Author: qiuxin_88 |
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Description: 通过将三维图像投影成2维ddr图像来实现2D-3D图像配准
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Size: 108976 |
Author: 张旭 |
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Description: 这是个跳舞机的源程序-This is a revolution of the source
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Size: 409426 |
Author: 王燕 |
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Description: SEED-DaVinci_EVM ddr 开发源代码
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Size: 37393 |
Author: eser |
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Description: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例
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Size: 25327 |
Author: shicheng342 |
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Description: 基于FPGA 实现DDR SDRAM的控制器
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Size: 474402 |
Author: 张宁 |
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Description: ddr 2 接口读写测试模块
ddr 2 接口读写测试模块
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Size: 126459 |
Author: 骑士 |
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Description: 移植好的支持MPC5200B处理器和DDR SDRAM以及PCF8563实时时钟和SM712显卡启动的u-boot源代码
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Size: 9977110 |
Author: XueTao |
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Description: DDR SRAM控制器的verilog完整设计文档(包含有完整的verilog源代码),
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Size: 475900 |
Author: lipengfei |
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Description: ALLEGRO 约束规则设置步骤(以DDR 为例),同样为pdf格式方便大家下载使用
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Size: 218416 |
Author: zhang |
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Description: ddr sdram 的控制代码,采用VHDL语言书写
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Size: 282097 |
Author: zxb |
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Description: ddr ram controller vhdl code
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Size: 55711 |
Author: heyong |
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Description: 关于DDR控制器方面的,可以看看,里面有较完整的代码和说明。
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Size: 39360 |
Author: yuhl |
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