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[Embeded-SCM Develop] ref-ddr-sdram-verilog.zip

Description: sdram的verilog的源码实现
Platform: | Size: 903683 | Author: | Hits:

[Embeded-SCM Develop] ref-ddr-sdram-vhdl.zip

Description:
Platform: | Size: 1031343 | Author: | Hits:

[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other resource] ddr_verilog_xilinx

Description: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131327 | Author: 陈旭 | Hits:

[Other resource] ddr

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 2317 | Author: 孙强 | Hits:

[Develop Tools] iptables 簡介

Description: iptables 簡介.rar ddr-iptables briefing. Rar ddr
Platform: | Size: 62125 | Author: 周平 | Hits:

[Other resource] EEPROM24CXX

Description: EEPROM 24CXX应用程序供参考 对EEPROM数据区读出（当前值=ADDR+WRC_<=0FFH），每进行一次读操作将使ADDR值减一；读出数据后程序将把该数据存入通用寄存器中，开始存放的地址由FSR的值指定（范例为30H），每进行一次读操作将使FSR的值加一；读出规定个数（由寄存器REC_给定，范例值为0FH）的数值后，结束读出，回main-EEPROM qi application for reference to the District EEPROM data read out (current value = A DDR WRC_
Platform: | Size: 1335 | Author: 风鹰 | Hits:

[Other resource] !ddr_sdram

Description: ddr sram的官方文档,介绍了ddr sram的使用及其接口等各方面的消息资料.
Platform: | Size: 452448 | Author: wang | Hits:

[File Operate] DDR_SDRAM_use_in_embedded

Description: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Platform: | Size: 237546 | Author: joucan | Hits:

[Other resource] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[Other resource] ddr_cntl_a_withtb

Description: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Platform: | Size: 2385568 | Author: yourname | Hits:

[Linux-Unix] tstSdram

Description: pnx1500 ddr test demo
Platform: | Size: 28742 | Author: 曾宏 | Hits:

[Other resource] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: | Size: 297475 | Author: mingming | Hits:

[Other resource] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 895594 | Author: 姚明 | Hits:

[OS Develop] jsjktbg1_mydown0315

Description: xilinx ddr controler
Platform: | Size: 11756 | Author: lanse | Hits:

[Other] memtest86+-1.30.tar

Description: ddr and sdram memory check,ddr and sdram memory check-ddr sdram memory and check, ddr sdram memory check and
Platform: | Size: 136002 | Author: wangdong | Hits:

[VHDL-FPGA-Verilog] xst_vlog_bl2cl25

Description: DDR 原厂IP核开源代码控制器vrilogHDL代码(xilinx ddr control xst)
Platform: | Size: 220160 | Author: happy2050 | Hits:

[DSP program] KeyStone_Memory_for_4G

Description: TI 6678DSP 4G ddr 简单测试，便以懒人使用。(TI 6678DSP 4G DDR is a simple test, it will be used by lazy people.)
Platform: | Size: 188416 | Author: nihao198 | Hits:

[VHDL-FPGA-Verilog] FPGA读取sd卡音频到DDR

Description: Xilinx FPGA读取sd卡音频到DDR，vivado实现
Platform: | Size: 17959013 | Author: 393975487@qq.com | Hits:

[Other] iMX DDR calibration

Description: DDr calibration process described
Platform: | Size: 501926 | Author: demonb | Hits:
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