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[DSP program] ddr

Description: davinci下DDR实例程序，可以帮助初学者学习davinci系列DSp。-the text is for the davinci .
Platform: | Size: 84992 | Author: zhangkun | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp851

Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: | Size: 408576 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
Platform: | Size: 680960 | Author: suyufeng | Hits:

[Other] rtl

Description: ddr controller in verilog-ddr controller in verilog...............
Platform: | Size: 69632 | Author: guanchuanjian | Hits:

[Software Engineering] DDR2_hardcore_userguide

Description: xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
Platform: | Size: 2324480 | Author: james | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR——SDRAM学习资料，DDR——SDRAM学习资料-DDR- SDRAM learning materials, DDR- SDRAM learning materials
Platform: | Size: 338944 | Author: ytqcom | Hits:

[VHDL-FPGA-Verilog] DDR_controller_verilog

Description: ddr的控制程序，用verilog实现的，非常的具体。-ddr
Platform: | Size: 623616 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] ddrsdram_verilog

Description: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
Platform: | Size: 751616 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_VHDL

Description: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.
Platform: | Size: 886784 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] tips_vhdl

Description: 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序，供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
Platform: | Size: 7177216 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[Disk Tools] ddr_contrl

Description: DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
Platform: | Size: 4096 | Author: leos | Hits:

[SCM] DDRcontrol

Description: DDR控制器的设计参考，包含有中文说明文档-DDR controller design for reference, including documentation in Chinese
Platform: | Size: 475136 | Author: 林果 | Hits:

[SCM] DDR2SDRAM

Description: 使用MIG工具生成DDR控制器的技术介绍-Using the MIG tool to generate the DDR Controller Technology
Platform: | Size: 10240 | Author: 林果 | Hits:

[source in ebook] xapp702

Description: 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
Platform: | Size: 216064 | Author: 林果 | Hits:

[Software Engineering] S3C6410_wince6.0

Description: S3C6410 wince6.0 DDR 从128MB 扩展为256MB-S3C6410 wince6.0 DDR expanded from 128MB to 256MB
Platform: | Size: 1024 | Author: 周远峰 | Hits:

[VHDL-FPGA-Verilog] doc17414x90

Description: ddr设计控制器，源代码！Verilog代码！-设计控制器，源代码！Verilog代码！
Platform: | Size: 646144 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] ddr2_controller

Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: | Size: 52224 | Author: yanxp | Hits:

[VHDL-FPGA-Verilog] Twister_DDR_SDRAM_Board_Manual

Description: Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
Platform: | Size: 1452032 | Author: SEED | Hits:
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