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[Other] ddr_ctrlv

Description: ddr ram controller vhdl code
Platform: | Size: 55296 | Author: heyong | Hits:

[Windows Develop] ddr_sdr_V1_0

Description: 关于DDR控制器方面的，可以看看，里面有较完整的代码和说明。-On the DDR controllers, you can see, there are more complete code and description.
Platform: | Size: 38912 | Author: yuhl | Hits:

[VHDL-FPGA-Verilog] rtl

Description: DDR控制器 已通过FPGA 验证 大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Platform: | Size: 52224 | Author: kin | Hits:

[DSP program] ddr2

Description: TI dm643 DDR 配置源代码,可以直接下载到板子上运行-TI dm643 DDR configuration source code, can be directly downloaded to the board to run
Platform: | Size: 5120 | Author: 张健 | Hits:

[Technology Management] W949D2BBAP01001W

Description: 华邦W949D2BBAP01001W ddr芯片spec。网上找不到的。-W949D2BBAP01001W ddr Winbond chip spec. Internet can not be found.
Platform: | Size: 823296 | Author: 徐钧 | Hits:

[Communication-Mobile] SmallCore_SDRAM

Description: MagicSopc DDR-Sdram
Platform: | Size: 576512 | Author: Rainy | Hits:

[SCM] DDR_SDRAM_DesignSummarize

Description: 基于Xilinx Spartan系列开发板的DDR SDRAM设计方案及经验总结!-Based on the Xilinx Spartan family of development boards and the DDR SDRAM design experience!
Platform: | Size: 338944 | Author: 曾娟丽 | Hits:

[Other] 128Mb_ddr

Description: 128Mb DDR verilog源程序-128Mb DDR verilog source code
Platform: | Size: 23552 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] Xil3S500E_Serial_Flash_v81

Description: 这是一个利用xilinx的macroblaze将用户程序由flash读取至ddr内存的例程，关键是bootloader的写法。-This is a use of Xilinx macroblaze the user program will read from flash memory to ddr routine, the key is the wording of bootloader.
Platform: | Size: 1334272 | Author: weichengguanzhe | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_verilog

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Platform: | Size: 752640 | Author: 宋珂 | Hits:

[Software Engineering] mx27ads_x33

Description: i.mx27开发板的整套详细原理图，包括：DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface, etc.
Platform: | Size: 741376 | Author: 清木 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Platform: | Size: 1021952 | Author: shroy | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[Other] DDR_allegro

Description: 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
Platform: | Size: 372736 | Author: 朱宝军 | Hits:

[Software Engineering] 20060510191318991

Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Platform: | Size: 2253824 | Author: 盛雪飞 | Hits:

[Linux-Unix] Hardware_Test_Programs

Description: ccs下对dm6446的测试程序，能够检测ddr,nandflash,uart,usb等硬件电路的裸板测试代码，包含库文件，板级gel文件，开发环境在TI ccs3.3下。-ccs on DM6446 testing procedures can detect ddr, nandflash, uart, usb hardware such as the bare circuit board to test the code, including library files, board-level gel documentation, development environment in the next TI ccs3.3.
Platform: | Size: 3568640 | Author: 王枫 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Platform: | Size: 474112 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] DDR

Description: leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
Platform: | Size: 752640 | Author: free | Hits:

[Software Engineering] K4H511638脰D

Description: Data Sheet 512Mb D-die DDR SDRAM Specification
Platform: | Size: 292864 | Author: Naeem | Hits:

[Other] testbench

Description: ddr sdram controller datd module source code
Platform: | Size: 3072 | Author: KrishnaKishore | Hits:
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