ddr

DDR_controller_verilog\doc\ddr_sdram.pdf
......................\model\mt46v4m16.v
......................\route\ddr_sdram.csf
......................\.....\ddr_sdram.esf
......................\.....\ddr_sdram.psf
......................\.....\ddr_sdram.quartus
......................\.....\ddr_sdram.vqm
......................\.....\pll1.v
......................\simulation\ddr_compile_all.v
......................\..........\ddr_sdram_tb.v
......................\..........\modelsim.ini
......................\..........\work\altclklock\verilog.psm
......................\..........\....\..........\_primary.dat
......................\..........\....\..........\_primary.vhd
......................\..........\....\ddr_command\verilog.psm
......................\..........\....\...........\_primary.dat
......................\..........\....\...........\_primary.vhd
......................\..........\....\......ntrol_interface\verilog.psm
......................\..........\....\.....................\_primary.dat
......................\..........\....\.....................\_primary.vhd
......................\..........\....\....data_path\verilog.psm
......................\..........\....\.............\_primary.dat
......................\..........\....\.............\_primary.vhd
......................\..........\....\....sdram\verilog.psm
......................\..........\....\.........\_primary.dat
......................\..........\....\.........\_primary.vhd
......................\..........\....\........._tb\verilog.psm
......................\..........\....\............\_primary.dat
......................\..........\....\............\_primary.vhd
......................\..........\....\mt46v4m16\verilog.psm
......................\..........\....\.........\_primary.dat
......................\..........\....\.........\_primary.vhd
......................\..........\....\pll1\verilog.psm
......................\..........\....\....\_primary.dat
......................\..........\....\....\_primary.vhd
......................\..........\....\_info
......................\.ource\altclklock.v
......................\......\ddr_Command.v
......................\......\ddr_control_interface.v
......................\......\ddr_data_path.v
......................\......\ddr_sdram.v
......................\......\Params.v
......................\......\pll1.v
......................\控制程序.txt
......................\simulation\work\altclklock
......................\..........\....\ddr_command
......................\..........\....\ddr_control_interface
......................\..........\....\ddr_data_path
......................\..........\....\ddr_sdram
......................\..........\....\ddr_sdram_tb
......................\..........\....\mt46v4m16
......................\..........\....\pll1
......................\..........\work
......................\doc
......................\model
......................\route
......................\simulation
......................\source
DDR_controller_verilog

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