xilinx of ddr sdram controller documentation

ddr_verilog_xilinx
..................\.recordref
..................\AutoConstraint_top.sdc
..................\backup
..................\compxlib.cfg
..................\coreip
..................\ddr_verilog_xilinx.ise
..................\ddr_verilog_xilinx.restore
..................\ddr_verilog_xilinx_xdb
..................\......................\tmp
..................\define.v
..................\doc
..................\...\ddr_xilinx.pdf
..................\glbl.v
..................\model.list
..................\modelsim.ini
..................\mt46v4m16.v
..................\readme.txt
..................\rpt_top.areasrr
..................\rpt_top_areasrr.htm
..................\run_options.txt
..................\stdout.log
..................\string_decode_fn.v
..................\synplicity.ucf
..................\syntmp
..................\......\sap.log
..................\......\top.plg
..................\......\top_flink.htm
..................\......\top_srr.htm
..................\......\top_toc.htm
..................\tb_top.v
..................\test.fdo
..................\test.udo
..................\test_wave.fdo
..................\top.edn
..................\top.fse
..................\top.htm
..................\top.map
..................\top.ncf
..................\top.prj
..................\top.sap
..................\top.sdc
..................\top.srd
..................\top.srm
..................\top.srr
..................\top.srs
..................\top.szr
..................\top.tlg
..................\top.ucf
..................\top_compile.tcl
..................\top_func.v
..................\top_map.tcl
..................\top_summary.html
..................\transcript
..................\traplog.tlg
..................\verif
..................\.....\top.vif
..................\vsim.wlf
..................\wave.do
..................\work
..................\....\addr_latch
..................\....\..........\_primary.dat
..................\....\..........\_primary.vhd
..................\....\brst_cntr
..................\....\.........\_primary.dat
..................\....\.........\_primary.vhd
..................\....\clk_dlls
..................\....\........\_primary.dat
..................\....\........\_primary.vhd
..................\....\controller
..................\....\..........\_primary.dat
..................\....\..........\_primary.vhd
..................\....\cslt_cntr
..................\....\.........\_primary.dat
..................\....\.........\_primary.vhd
..................\....\data_dly
..................\....\........\_primary.dat
..................\....\........\_primary.vhd
..................\....\data_path
..................\....\.........\_primary.dat
..................\....\.........\_primary.vhd
..................\....\ddr_ctlr
..................\....\........\_primary.dat
..................\....\........\_primary.vhd
..................\....\ddr_dq_io_16
..................\....\............\_primary.dat
..................\....\............\_primary.vhd
..................\....\ddr_iob_ff
..................\....\..........\_primary.dat
..................\....\..........\_primary.vhd
..................\....\glbl
..................\....\....\_primary.dat
..................\....\....\_primary.vhd
..................\....\mt46v4m16
..................\....\.........\_primary.dat
..................\....\.........\_primary.vhd
..................\....\rcd_cntr
..................\....\........\_primary.dat
..................\....\........\_primary.vhd
..................\....\test

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