DDR SDRAM\4_01_02_04R13.pdf
.........\DDR SDRAM\mem_interface_top.txt
.........\.........\mem_interface_top_addr_gen_0.txt
.........\.........\mem_interface_top_backend_fifos_0.txt
.........\.........\mem_interface_top_backend_rom_0.txt
.........\.........\mem_interface_top_cmp_rd_data_0.txt
.........\.........\mem_interface_top_controller_iobs_0.txt
.........\.........\mem_interface_top_data_gen_16.txt
.........\.........\mem_interface_top_data_path_0.txt
.........\.........\mem_interface_top_data_path_iobs_0.txt
.........\.........\mem_interface_top_data_tap_inc.txt
.........\.........\mem_interface_top_data_write_0.txt
.........\.........\mem_interface_top_ddr_controller_0.txt
.........\.........\mem_interface_top_idelay_ctrl.txt
.........\.........\mem_interface_top_infrastructure.txt
.........\.........\mem_interface_top_infrastructure_iobs_0.txt
.........\.........\mem_interface_top_iobs_0.txt
.........\.........\mem_interface_top_main_0.txt
.........\.........\mem_interface_top_parameters_0.txt
.........\.........\mem_interface_top_pattern_compare8.txt
.........\.........\mem_interface_top_RAM_D_0.txt
.........\.........\mem_interface_top_rd_data_0.txt
.........\.........\mem_interface_top_rd_data_fifo_0.txt
.........\.........\mem_interface_top_rd_wr_addr_fifo_0.txt
.........\.........\mem_interface_top_tap_ctrl_0.txt
.........\.........\mem_interface_top_tap_logic_0.txt
.........\.........\mem_interface_top_test_bench_0.txt
.........\.........\mem_interface_top_top_0.txt
.........\.........\mem_interface_top_user_interface_0.txt
.........\.........\mem_interface_top_v4_dm_iob.txt
.........\.........\mem_interface_top_v4_dqs_iob.txt
.........\.........\mem_interface_top_v4_dq_iob.txt
.........\.........\mem_interface_top_wr_data_fifo_16.txt
.........\.........\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
.........\DDR SDRAM控制器的FPGA实现.pdf
.........\DDR SDRAM设计及调试经验总结.pdf
.........\DDR System Design Considerations.pdf
.........\ddrregrev1.2.pdf
.........\DDR_SDRAM_controller\doc\ddr_sdram.pdf
.........\....................\help.txt
.........\....................\model\mt46v4m16.vhd
.........\....................\.....\mti_pkg.vhd
.........\....................\PCB资源网.txt
.........\....................\route\ddr_sdram.csf
.........\....................\.....\ddr_sdram.esf
.........\....................\.....\ddr_sdram.quartus
.........\....................\.....\ddr_sdram.vqm
.........\....................\.....\pll1.vhd
.........\....................\simulation\APEX20KE_MF.VHD
.........\....................\..........\ddr_command.vhd
.........\....................\..........\ddr_control_interface.vhd
.........\....................\..........\ddr_data_path.vhd
.........\....................\..........\ddr_sdram.vhd
.........\....................\..........\ddr_sdram_tb.vhd
.........\....................\..........\io_utils.vhd
.........\....................\..........\lpm_pack.vhd
.........\....................\..........\modelsim.ini
.........\....................\..........\mt46v4m16.vhd
.........\....................\..........\mti_pkg.bak
.........\....................\..........\mti_pkg.vhd
.........\....................\..........\pll1.vhd
.........\....................\..........\readme.txt
.........\....................\..........\stdlogar.vhd
.........\....................\..........\util1164.vhd
.........\....................\..........\wave.do
.........\....................\..........\.ork\altcam\behave.dat
.........\....................\..........\....\......\behave.psm
.........\....................\..........\....\......\_primary.dat
.........\....................\..........\....\....lklock\behavior.dat
.........\....................\..........\....\..........\behavior.psm
.........\....................\..........\....\..........\_primary.dat
.........\....................\..........\....\...lvds_rx\behavior.dat
.........\....................\..........\....\..........\behavior.psm
.........\....................\..........\....\..........\_primary.dat
.........\....................\