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[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[VHDL-FPGA-Verilog] USB2.0

Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: | Size: 3567616 | Author: PETER | Hits:

[VHDL-FPGA-Verilog] ADS7852

Description: FPGA采用VHDL语言驱动ADS7852的程序,-FPGA and ADS7852
Platform: | Size: 239616 | Author: xila | Hits:

[VHDL-FPGA-Verilog] max197

Description: FPGA实现MAX197读写程序，经过验证-FPGA control 12bAD max197
Platform: | Size: 3072 | Author: 刘义红 | Hits:

[VHDL-FPGA-Verilog] CHICAGO5Manual

Description: 高科技的发展使芯片设计不再是半导体工业的领域，现场可编程逻辑阵列（FPGA）的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生，使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器，迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, field programmable logic arrays (FPGA) through the emergence of chip design software to quickly achieve the possible. This system is a broad global engineering and technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.
Platform: | Size: 258048 | Author: 童志通 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: 学习FPGA很有价值的27个例子,以VHDL为例子，也可以用verilog-27examples of fpga for the leaner
Platform: | Size: 1278976 | Author: 方主 | Hits:

[Other] deep_LabVIEW_FPGA

Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备，为测量和控制系统中整合FPGA 技术的 灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑 功能，您不需要任何的有关底层硬件描述语言(HDLs)的知识，如VHDL 或是Verilog，也不需要了解板 卡级硬件设计，就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外，LabVIEW还 可以让您轻松地集成图象采集/分析、运动控制，以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries.
Platform: | Size: 274432 | Author: 侯yl | Hits:

[source in ebook] ds18b20

Description: 艾米电子FPGA18b20的verilog源代码-aimi stdio fpga
Platform: | Size: 72704 | Author: 王萍 | Hits:

[VHDL-FPGA-Verilog] VERILOG-jpeg

Description: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Platform: | Size: 103424 | Author: ken | Hits:

[VHDL-FPGA-Verilog] GMSK

Description: GMSK的FPGA实现程序，全数字GMSK实现方案。-GMSK FPGA-implementation process, all-digital GMSK implementations.
Platform: | Size: 1024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] tlc2543AND11channel

Description: 11路串行AD采集芯片TLC2543，12BIT精度输出，100Khz，采用VERILOG HDL编写，占用200个LE-11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
Platform: | Size: 32768 | Author: chenwl | Hits:

[VHDL-FPGA-Verilog] crc16_8

Description: crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
Platform: | Size: 1024 | Author: chenk | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] clock

Description: 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
Platform: | Size: 2747392 | Author: 曹丽娜 | Hits:

[VHDL-FPGA-Verilog] Verilog-pci

Description: PCI的FPGA实现，使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
Platform: | Size: 5510144 | Author: zxc | Hits:

[VHDL-FPGA-Verilog] MEDIAN.v

Description: fpga 的 median的verilog实现-median of verilog implementation
Platform: | Size: 1024 | Author: xyz | Hits:

[VHDL-FPGA-Verilog] QAM

Description: 16qam调制器的FPGA实现。使用Verilog实现全数字16-QAM调制器。-16qam Modulator FPGA. Use Verilog for full digital 16-QAM modulator.
Platform: | Size: 2048 | Author: 张维 | Hits:

[USB develop] usbFPGAconnect

Description: 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program
Platform: | Size: 7154688 | Author: 梁先国 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:
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