sobel Adopted verilog language realizes edge detec

Title: sobel

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
10kb
Update:
2012-11-26
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0 Times
Uploaded by:
wkd

Description: Adopted verilog language realizes sobel edge detection in image processing algorithm

Downloaders recently: [More information of uploader wkd]

To Search: sobel vhdl sobel verilog sobel vhdl sobel edge detection verilog sobel FPGA Verilog EDGE DEtection verilog sobel edge detection FPGA edge detection in verilog

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[sobel] - SOBEL FILTER IN VHDL
[63535312DCTofJPEG] - Verilog code using JPEG compression enco
[edge_detector] - image edge detection

File list (Check if you may need any files):

sobel程序\abs.v
.........\data_grads.v
.........\fe_data3by3.v
.........\fe_fifo1.v
.........\fe_fifo2.v
.........\fe_generater_mode3by3.v
.........\Grads.v
.........\Gx_grad.v
.........\Gy_grad.v
sobel程序

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