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[VHDL-FPGA-Verilog] zigzag

Description: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Platform: | Size: 7168 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] CPLD_Design_50

Description: CPLD实用设计50例，非常经典的CPLD设计，包含50个实际的典型应用，涉及直流电机PWM驱动，编码等内容，有了这50例，举一反三，就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications
Platform: | Size: 7625728 | Author: 刘工 | Hits:

[VHDL-FPGA-Verilog] config_dac

Description: Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified
Platform: | Size: 274432 | Author: 强冰 | Hits:

[VHDL-FPGA-Verilog] ADCtest

Description: 利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the
Platform: | Size: 589824 | Author: ticklay | Hits:

[VHDL-FPGA-Verilog] DCT

Description: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
Platform: | Size: 15400960 | Author: alison | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.
Platform: | Size: 1736704 | Author: 姚大雷 | Hits:

[Other] fpgaandveriloghdl

Description: FPGA中嵌中高级课件,非常有用的课件，对于新手和老手都有很大的帮助！希望大家看了以后能够大大的提高自己的水平！-FPGA in the embedded high-class courseware, the courseware is very useful for both novice and veteran of great help! I hope everyone saw the future can greatly improve the level of their own!
Platform: | Size: 11936768 | Author: 乔 | Hits:

[VHDL-FPGA-Verilog] RSdecoder

Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
Platform: | Size: 13312 | Author: 陈臣 | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[VHDL-FPGA-Verilog] S8_VGA

Description: VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动-VGA display interface Verilog control procedures. Control for VGA display driver
Platform: | Size: 1127424 | Author: zl.yin | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 基于FPGA嵌入式开发实现的VGA接口，已经验证通过。-FPGA-based embedded development to achieve the VGA interface, has been adopted to verify.
Platform: | Size: 4361216 | Author: john | Hits:

[VHDL-FPGA-Verilog] (fpga)sdram

Description: verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
Platform: | Size: 19935232 | Author: ch | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
Platform: | Size: 1216512 | Author: zwt | Hits:

[VHDL-FPGA-Verilog] TLC549

Description: verilog TLC549AD采样程序 ，速度200K，在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
Platform: | Size: 1024 | Author: 张建中 | Hits:

[VHDL-FPGA-Verilog] CORDIC_ATAN

Description: 使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代-Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations
Platform: | Size: 1024 | Author: 小米 | Hits:

[VHDL-FPGA-Verilog] write_rd

Description: 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
Platform: | Size: 91136 | Author: hanmy | Hits:

[VHDL-FPGA-Verilog] FPGAkaifashilidaohang

Description: 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design -err
Platform: | Size: 1566720 | Author: 黑洞 | Hits:

[VHDL-FPGA-Verilog] sin.tar

Description: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:
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