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[VHDL-FPGA-Verilog] Tun2CNk2

Description: FPGA实现DSP的Verilog 示例-FPGA realization of DSP-Verilog Example
Platform: | Size: 331776 | Author: wanghua | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] alu3

Description: 用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作-Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating
Platform: | Size: 203776 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] 4bit.elock

Description: 4位电子密码锁，有详细的步骤说明，有功能仿真图，值得一看-4 electronic code locks, has detailed the steps that have functional simulation map, worth a visit
Platform: | Size: 458752 | Author: 李里 | Hits:

[VHDL-FPGA-Verilog] 76_PID

Description: 一个非常好的电机转速控制器VHDL源代码设计-A very good motor speed controller VHDL design source code
Platform: | Size: 2048 | Author: linew | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] md5

Description: MD5 算法在Xilinx FPGA上的实现，希望对大家有用。-MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.
Platform: | Size: 10240 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilog] UART_rec

Description: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[Compress-Decompress algrithms] masterspiverilog

Description: spi总线控制器的fpga实现 verilog源代码及测试-spi bus controller realize the FPGA Verilog source code and test
Platform: | Size: 180224 | Author: sang | Hits:

[Communication] viterbidecoder

Description: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。-2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
Platform: | Size: 1665024 | Author: Wayne | Hits:

[VHDL-FPGA-Verilog] rs422

Description: rs422接 VHDL语言编写 chipescope仿真通过-RS422 access chipescope language VHDL simulation through
Platform: | Size: 975872 | Author: 殷凤平 | Hits:

[VHDL-FPGA-Verilog] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Platform: | Size: 975872 | Author: 杨林成 | Hits:

[VHDL-FPGA-Verilog] at24c02

Description: 基于FPGA的24C02驱动程序，使用有限状态机～结构完整，测试通过。-FPGA-based 24C02 driver, the use of finite state machine ~ structural integrity of the test.
Platform: | Size: 1156096 | Author: edjj | Hits:

[Documents] fir

Description: 线性相位FIR滤波器（17阶）的VHDL语言设计 功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Platform: | Size: 148480 | Author: jingjing | Hits:

[VHDL-FPGA-Verilog] cordic

Description: cordic verilog 程序及仿真结果 8级流水线-cordic verilog simulation results procedures and eight lines
Platform: | Size: 1024 | Author: elisen | Hits:

[VHDL-FPGA-Verilog] camera.tar

Description: 摄像头的硬件函数，ip核，用于xilinx公司的virtex4 fpga-Camera
Platform: | Size: 416768 | Author: 惠普 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 14336 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 4096 | Author: caesar | Hits:
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