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[VHDL-FPGA-Verilog] HPI

Description: 基于CPLD/FPGA器件的HPI接口程序 难能可贵-HPI based on CPLD/FPGA instrument
Platform: | Size: 2268160 | Author: ld | Hits:

[VHDL-FPGA-Verilog] xapp856

Description: 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
Platform: | Size: 556032 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] ep_rom

Description: 采用VerilogHdl语言编写的，介于FPGA的EPROM的开发读写-VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
Platform: | Size: 1024 | Author: Kevin Yu | Hits:

[VHDL-FPGA-Verilog] cpu_lynn

Description: Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
Platform: | Size: 11264 | Author: wei | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] flash

Description: fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
Platform: | Size: 1024 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL

Description: FPGA采用模块工程文件QUARTUS II工程、ADC0809、电机控制PWM、LCD12864显示控制、UART_VHDL-FPGA module QUARTUS II project engineering documents, ADC0809, motor control PWM, LCD12864 display control, UART_VHDL
Platform: | Size: 238592 | Author: wangzhaohui | Hits:

[VHDL-FPGA-Verilog] AD

Description: FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。-FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.
Platform: | Size: 1980416 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] DA

Description: FPGA控制DAC2807的源文件，Verilog。附有简单文档-FPGA control DAC2807 source, Verilog. A simple document
Platform: | Size: 1629184 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] FFT_verilog

Description: verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Platform: | Size: 618496 | Author: culun | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS

Description: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[VHDL-FPGA-Verilog] FPGA-IIC

Description: 在FPGA内，实现IIC数据接口。verilog源代码-In the FPGA, the realization of IIC data interfaces. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[Other] UART_VHDL

Description: 由于微电子学和计算机科学的迅速发展，给EDA(电子设计自动化)行业带来了巨大的变化。特别是进入20世纪90年代后，电子系统已经从电路板级系统集成发展成为包括ASIC、FPGA/CPLD和嵌入系统的多种模式。可以说EDA产业已经成为电子信息类产品的支柱产业。EDA之所以能蓬勃发展的关键因素之一就是采用了硬件描述语言(HDL)描述电路系统。就FPGA和CPLD开发而言，比较流行的HDL主要有Verilog HDL、VHDL、ABEL-HDL和 AHDL 等，其中VHDL和Verilog HDL因适合标准化的发展方向而最终成为IEEE标准。-As the microelectronics and the rapid development of computer science, to the EDA (electronic design automation) industry, has brought great changes. Especially the beginning of the 20th century, 90 years, the electronic system has moved from the circuit board-level systems integration to develop into, including ASIC, FPGA/CPLD and embedded systems a variety of modes. Can be said that EDA industry, electronic information products has become a pillar industry. EDA has been able to flourish, one of the key factors is the use of a hardware description language (HDL) description of the electronic circuitry. On the FPGA and CPLD development, the more popular HDL mainly Verilog HDL, VHDL, ABEL-HDL, and AHDL etc., in which VHDL and Verilog HDL because of the direction for the development of standardization eventually become IEEE standard.
Platform: | Size: 290816 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] spitoi2s3

Description: spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
Platform: | Size: 5120 | Author: steny | Hits:

[VHDL-FPGA-Verilog] vga

Description: verilog file , FPGA controll vga display- verilog file , FPGA controll vga display
Platform: | Size: 203776 | Author: panchao | Hits:

[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: h264 vhdl/verilog implementation on FPGA platform
Platform: | Size: 16850944 | Author: ravi | Hits:

[VHDL-FPGA-Verilog] module_dem

Description: 用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现-Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation
Platform: | Size: 6068224 | Author: yu | Hits:

[VHDL-FPGA-Verilog] ads7822

Description: ads7822的verilog驱动 fpga芯片为altera公司的ep2c35， 程序调试过好使-ads7822 of verilog-driven
Platform: | Size: 1411072 | Author: 王乐 | Hits:

[VHDL-FPGA-Verilog] Verilog_UDP

Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Platform: | Size: 125952 | Author: 龙也 | Hits:

[Embeded-SCM Develop] c_FPGA

Description: RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
Platform: | Size: 1249280 | Author: 洪依 | Hits:
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