Description: 2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
- [Viterbi_v] - Viterbi Algorithm Verilog source code.
- [easy_pll] - easy pll, good PLL (phase-locked loop de
- [4bit.elock] - 4 electronic code locks, has detailed th
- [20] - FPGA platform for voice communications d
- [RS(31-19-6)] - reed-solomon decoder. A total of seven p
- [rs_encoder] - This code is used for DVB systems channe
- [TBD_Viterbi] - Weak for radar target detection algorith
- [juanjiviterbi1] - viterbi convolutional code encoding, dec
- [channel_coding] - WIMAX standards applied under the channe
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