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[VHDL-FPGA-Verilog] cpu

Description: 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
Platform: | Size: 2196480 | Author: mollyma | Hits:

[VHDL-FPGA-Verilog] alu

Description: arithmetical-logic unit design in Verilog
Platform: | Size: 1024 | Author: Iuliana, Chiuchisan | Hits:

[Other] alu

Description: ALU运算器实现基本算术运算+,-,*,/和逻辑运算-ALU with the basic math function and logic function
Platform: | Size: 2048 | Author: hawa | Hits:

[VHDL-FPGA-Verilog] ALU

Description: David pattern 的ALU模型编码-David pattern in the ALU model code
Platform: | Size: 273408 | Author: aguang | Hits:

[VHDL-FPGA-Verilog] 74181ALU

Description: alu功能。实现计算机的数字运算。运用的是74181芯片-alu function. The number of computer-based operations. Use the 74181 chip. .
Platform: | Size: 1024 | Author: 刘墉 | Hits:

[VHDL-FPGA-Verilog] alu32bit

Description: verilog hdl alu module it is 32bit alu and 1bit alu
Platform: | Size: 368640 | Author: park | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 一个全的alu，可以学些东西，对初学者有用-alu, can learn some things, useful for beginners
Platform: | Size: 354304 | Author: 高翔 | Hits:

[VHDL-FPGA-Verilog] Designs

Description: design files in verilog, alu, array mult, carry shift etc.
Platform: | Size: 37888 | Author: p2p_123 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 实现16-bits alu功能，其中包含按位逻辑运算，加减等运算。
Platform: | Size: 19456 | Author: 张卫华 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: VHDL code for 3 bit ALU
Platform: | Size: 10240 | Author: vasu | Hits:

[VHDL-FPGA-Verilog] alu

Description: 实现五位加法器功能，还有ALU的程序模块！同时有四位全加器的功能模块！-Adder to achieve five functions, as well as program modules ALU! At the same time there are four full-adder modules!
Platform: | Size: 1024 | Author: qixia | Hits:

[VHDL-FPGA-Verilog] alu

Description: 运算器实现，运用Veriolog语言，编程实现，无错误，顺利编译，可执行，仿真图正确~-ALU implementation, the use of Veriolog language, programming, error-free, smooth build, executable, simulation plan correctly ~
Platform: | Size: 220160 | Author: uyuy0401 | Hits:

[Other] ALU_Design

Description: 通过maxplus完成的ALU设计，乘法、除法、加减法以及常见的逻辑运算的功能都基本得到实现，其中乘除法使用的是阵列乘除-Completed by maxplus ALU design, multiplication, division, addition and subtraction and common features are the basic logic operations are achieved, which is the array multiplication and division using multiplication and division
Platform: | Size: 433152 | Author: qiren | Hits:

[VHDL-FPGA-Verilog] ARM32ALU

Description: VHDL ARM 32位ALU的设计，基于Quaryus II平台-VHDL ARM 32 位 ALU design platform based on Quaryus II
Platform: | Size: 287744 | Author: 逆天之刃 | Hits:

[VHDL-FPGA-Verilog] alu32

Description: 32 bit ALU design using VHDL code for Xilinx ISE Foundation
Platform: | Size: 1024 | Author: Bruno Frankelli | Hits:

[VHDL-FPGA-Verilog] alu

Description: VHDL描述的alu，可以进行基本的运算，在quartus2环境下运行。实验课作业。-VHDL description of the alu, the basic operations can be carried out in quartus2 environments. Experimental course work.
Platform: | Size: 2027520 | Author: EMMILY | Hits:

[VHDL-FPGA-Verilog] alu

Description: 用VHDL语言编写的CPU当中的ALU模块，可是实现十条指令-CPU using VHDL languages among the ALU module, but to achieve ten instructions
Platform: | Size: 1024 | Author: wu | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 4位ALU，实现简单的ALU，包含一些简单的指令-ALU
Platform: | Size: 293888 | Author: 陈军 | Hits:

[VHDL-FPGA-Verilog] 3_3_mean_diltter(ALU)

Description: 3*3均值滤波的VHDL语言实现的工程，对红外图像进行有效的去噪处理。这是其中的ALU模块，专门用来测试其延迟状况的模块。-3* 3 mean filter VHDL language works effectively on the infrared image denoising. This is one of the ALU module, designed to test the status of the module delay.
Platform: | Size: 749568 | Author: gglight | Hits:

[VHDL-FPGA-Verilog] ALU

Description: sources code to program an microprocessor ALU
Platform: | Size: 5120 | Author: yang | Hits:

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[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] alu

[Other] alu

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] 74181ALU

[VHDL-FPGA-Verilog] alu32bit

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] Designs

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu

[Other] ALU_Design

[VHDL-FPGA-Verilog] ARM32ALU

[VHDL-FPGA-Verilog] alu32

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] 3_3_mean_diltter(ALU)

[VHDL-FPGA-Verilog] ALU

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