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[VHDL-FPGA-Verilog] alu-4bit DL : 0: alu包含各种运算功能，有点事现对于其他的程序，面积较小-it has a smaller square compared with othe program.
Date : 2025-07-13 Size : 1kb User : 谌敏飞
[VHDL-FPGA-Verilog] Design-And-Implementation-Of-64-Bit-ALU-Using-VHD DL : 0: Design And Implementation Of 64 Bit ALU Using VHDL
Date : 2025-07-13 Size : 13kb User : saipraveen
[VHDL-FPGA-Verilog] ALU DL : 0: 一个芯片内ALU的vhdl程序简单描述。-The VHDL discription of a chip
Date : 2025-07-13 Size : 2kb User : 姚江超
[VHDL-FPGA-Verilog] ALU DL : 0: VHDL设计的ALU，可以添加到CPU的编写者-VHDL lanuage design for ALU
Date : 2025-07-13 Size : 903kb User : 李峥
[VHDL-FPGA-Verilog] alu DL : 0: Verilog,PIC系列ALU设计，加法、减法、逻辑运算，二进制调整-Verilog,PIC ALU Design ADD SUB XOR AND
Date : 2025-07-13 Size : 1kb User : yueweijie
[VHDL-FPGA-Verilog] ALU DL : 0: 11条指令MIPS指令系统CPU中的ALU设计-11 instruction in the MIPS instruction ALU design in the system CPU
Date : 2025-07-13 Size : 1kb User : Yves Hu
[VHDL-FPGA-Verilog] design-and-implementation-of-64-bit-alu-using-vhd DL : 0: 64-bit ALU design to implement simple application program
Date : 2025-07-13 Size : 1.56mb User : siva
[VHDL-FPGA-Verilog] ALU DL : 0: ALU 与ALU控制器实验 VHDL Verilog 语言设计-ALU VHDL Verilog
Date : 2025-07-13 Size : 1kb User : abc
[VHDL-FPGA-Verilog] alu DL : 0: module alu (ina,inb,ALU_BUS,S,cout,y,clk) input[7:0] ina input[7:0] inb input ALU_BUS,clk input[2:0] S output cout output[7:0] y reg cout reg[7:0] y always @(posedge clk) begin if(ALU_BUS) begin case(S) 3 b000:{cout,y}=ina+inb 3 b001:{cout,y}=ina-inb 3 b010:{cout,y}=ina*inb 3 b011:{cout,y}=ina/inb 3 b100:y=ina&&inb 3 b101:y=ina||inb 3 b110:y=~inb 3 b111:y=ina^inb default:y=8 b00000000 endcase end else begin y=8 bZZZZZZZZ end end endmodule -module alu (ina, inb, ALU_BUS, S, cout, y, clk) input [7:0] ina input [7:0] inb input ALU_BUS, clk input [2:0] S output cout output [7:0] y reg cout reg [7:0] y always @ (posedge clk) begin if (ALU_BUS) begin case (S) 3' b000: {cout, y} = ina+inb 3' b001 : {cout, y} = ina-inb 3' b010: {cout, y} = ina* inb 3' b011: {cout, y} = ina/inb 3' b100: y = ina & & inb 3' b101 : y = ina | | inb 3' b110: y = ~ inb 3' b111: y = ina ^ inb default: y = 8' b00000000 endcase end else begin y = 8' bZZZZZZZZ end end endmodule
Date : 2025-07-13 Size : 468kb User : suhuhu
[VHDL-FPGA-Verilog] alu DL : 0: ALU 嵌入式单片机模块化 ALU实现-ALU embedded microcontroller modular ALU to achieve
Date : 2025-07-13 Size : 7kb User : xue ling
[Software Engineering] ALU-design DL : 0: ALU design with circuit maker
Date : 2025-07-13 Size : 99kb User : no_name
[Other] alu DL : 0: 一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算-alu module
Date : 2025-07-13 Size : 1kb User : Dora Yu
[Software Engineering] alu DL : 0: THIS VHDL CODE FOR ALU-THIS IS VHDL CODE FOR ALU
Date : 2025-07-13 Size : 1kb User : dhaval
[ELanguage] ALU DL : 0: Computer Architecture ALU
Date : 2025-07-13 Size : 1kb User : Ferial
[Editor] ALU DL : 0: ALU mips to development MIPs
Date : 2025-07-13 Size : 1kb User : ds1ds1
[source in ebook] ALU DL : 0: 实现ALU的运算用ACTIVE软件实现-ALU operation ACTIVE software implementation
Date : 2025-07-13 Size : 39kb User : henhe
[VHDL-FPGA-Verilog] alu DL : 0: It is 32 bit ALU code in Verilog HDL programming Language
Date : 2025-07-13 Size : 1kb User : srikanth
[Software Engineering] ALU DL : 0: 计算机ALU的verilog设计，能够实现加减与或运算-Computer ALU verilog design can add and subtract with or computing
Date : 2025-07-13 Size : 2kb User : hello
[VHDL-FPGA-Verilog] alu DL : 0: An ALU with two inputs a and b and four basic ALU functions: output=a+1 or a+b+1 or b or a+b. Using a 2 bit input "sel" to select one function.
Date : 2025-07-13 Size : 1kb User : cry
[Other] ALU DL : 0: MIPS ALU written using Verilog HDL. Computer structure project
Date : 2025-07-13 Size : 3kb User : viet

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