Search - alu - CodeBus

[VHDL-FPGA-Verilog] alu-4bit

Description: alu包含各种运算功能，有点事现对于其他的程序，面积较小-it has a smaller square compared with othe program.
Platform: | Size: 1024 | Author: 谌敏飞 | Hits:

[VHDL-FPGA-Verilog] Design-And-Implementation-Of-64-Bit-ALU-Using-VHD

Description: Design And Implementation Of 64 Bit ALU Using VHDL
Platform: | Size: 13312 | Author: saipraveen | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 一个芯片内ALU的vhdl程序简单描述。-The VHDL discription of a chip
Platform: | Size: 2048 | Author: 姚江超 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: VHDL设计的ALU，可以添加到CPU的编写者-VHDL lanuage design for ALU
Platform: | Size: 924672 | Author: 李峥 | Hits:

[VHDL-FPGA-Verilog] alu

Description: Verilog,PIC系列ALU设计，加法、减法、逻辑运算，二进制调整-Verilog,PIC ALU Design ADD SUB XOR AND
Platform: | Size: 1024 | Author: yueweijie | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 11条指令MIPS指令系统CPU中的ALU设计-11 instruction in the MIPS instruction ALU design in the system CPU
Platform: | Size: 1024 | Author: Yves Hu | Hits:

[VHDL-FPGA-Verilog] design-and-implementation-of-64-bit-alu-using-vhd

Description: 64-bit ALU design to implement simple application program
Platform: | Size: 1639424 | Author: siva | Hits:

[VHDL-FPGA-Verilog] ALU

Description: ALU 与ALU控制器实验 VHDL Verilog 语言设计-ALU VHDL Verilog
Platform: | Size: 1024 | Author: abc | Hits:

Description: module alu (ina,inb,ALU_BUS,S,cout,y,clk) input[7:0] ina input[7:0] inb input ALU_BUS,clk input[2:0] S output cout output[7:0] y reg cout reg[7:0] y always @(posedge clk) begin if(ALU_BUS) begin case(S) 3 b000:{cout,y}=ina+inb 3 b001:{cout,y}=ina-inb 3 b010:{cout,y}=ina*inb 3 b011:{cout,y}=ina/inb 3 b100:y=ina&&inb 3 b101:y=ina||inb 3 b110:y=~inb 3 b111:y=ina^inb default:y=8 b00000000 endcase end else begin y=8 bZZZZZZZZ end end endmodule -module alu (ina, inb, ALU_BUS, S, cout, y, clk) input [7:0] ina input [7:0] inb input ALU_BUS, clk input [2:0] S output cout output [7:0] y reg cout reg [7:0] y always @ (posedge clk) begin if (ALU_BUS) begin case (S) 3' b000: {cout, y} = ina+inb 3' b001 : {cout, y} = ina-inb 3' b010: {cout, y} = ina* inb 3' b011: {cout, y} = ina/inb 3' b100: y = ina & & inb 3' b101 : y = ina | | inb 3' b110: y = ~ inb 3' b111: y = ina ^ inb default: y = 8' b00000000 endcase end else begin y = 8' bZZZZZZZZ end end endmodule
Platform: | Size: 479232 | Author: suhuhu | Hits:

[VHDL-FPGA-Verilog] alu

Description: ALU 嵌入式单片机模块化 ALU实现-ALU embedded microcontroller modular ALU to achieve
Platform: | Size: 7168 | Author: xue ling | Hits:

[Software Engineering] ALU-design

Description: ALU design with circuit maker
Platform: | Size: 101376 | Author: no_name | Hits:

[Other] alu

Description: 一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算-alu module
Platform: | Size: 1024 | Author: Dora Yu | Hits:

[Software Engineering] alu

Description: THIS VHDL CODE FOR ALU-THIS IS VHDL CODE FOR ALU
Platform: | Size: 1024 | Author: dhaval | Hits:

[ELanguage] ALU

Description: Computer Architecture ALU
Platform: | Size: 1024 | Author: Ferial | Hits:

[Editor] ALU

Description: ALU mips to development MIPs
Platform: | Size: 1024 | Author: ds1ds1 | Hits:

[Other] ALU

Description: MIPS ALU written using Verilog HDL. Computer structure project
Platform: | Size: 3072 | Author: viet | Hits:

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[VHDL-FPGA-Verilog] alu-4bit

[VHDL-FPGA-Verilog] Design-And-Implementation-Of-64-Bit-ALU-Using-VHD

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] design-and-implementation-of-64-bit-alu-using-vhd

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu

[Software Engineering] ALU-design

[Other] alu

[Software Engineering] alu

[ELanguage] ALU

[Editor] ALU

[source in ebook] ALU

[VHDL-FPGA-Verilog] alu

[Software Engineering] ALU

[VHDL-FPGA-Verilog] alu

[Other] ALU

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