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[Windows Develop] ALU_32

Description: 32 bit ALU design,LU Operations: This input specifies the ALU operation to be used during the acquisition process. The ALU operations are divided into logical operations and two classes of arithmetic operations. The two classes of arithmetic operations vary in how the CARRYIN register on the frame grabber card is set. A list of the 48 operations is given below:
Platform: | Size: 1024 | Author: madhawa | Hits:

[Embeded-SCM Develop] LAB6

Description: 實現 74381 ALU IC 和 BCD 顯示的功能，並燒錄到板 子上驗證功能。-Achieve the 74381 ALU IC and BCD display function, and burn them to board on the authentication function.
Platform: | Size: 1159168 | Author: 徐小華 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 算数逻辑单元，实现算数加、减，加1、减1运算和逻辑与、或、非和传递-Arithmetic logic unit, to achieve arithmetic add, subtract, plus one, minus one operation and logical AND, OR, and transmission of non-
Platform: | Size: 303104 | Author: 龙一 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: ALU 内附 ALU op code 对照表格-ALU control forms included ALU op code
Platform: | Size: 287744 | Author: 赵彦 | Hits:

[VHDL-FPGA-Verilog] ALUALUcontrol

Description: 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Platform: | Size: 1060864 | Author: 于伟 | Hits:

[Software Engineering] alufinal

Description: alu circuit diagram for computer
Platform: | Size: 6144 | Author: prince | Hits:

[VHDL-FPGA-Verilog] ALU

Description: alu 模块，算术逻辑单元，实现简单的控制模块，有最基本的几条指令-alu instruction
Platform: | Size: 1024 | Author: henin | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl code for alu and detemines the basic components of alu unit in cpu system
Platform: | Size: 1024 | Author: basheer | Hits:

[VHDL-FPGA-Verilog] 4

Description: simple code based on verilog shifter , cla ,clg , ALU , PC
Platform: | Size: 3072 | Author: Tera | Hits:

[VHDL-FPGA-Verilog] alu_project

Description: ALU using VHDL project
Platform: | Size: 26624 | Author: msh2003 | Hits:

[Embeded-SCM Develop] VHDLmipsPipeline

Description: 32 位MIP流水线CPU设计，5 stage，代码详细，包括ALU,存储器,寄存器等，是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
Platform: | Size: 561152 | Author: suborong | Hits:

[Other] 32Bitaludesign

Description: Design of simple 32 bit alu for SPARTAN 3 paltform
Platform: | Size: 1024 | Author: Ammankumar | Hits:

[Mathimatics-Numerical algorithms] ALU

Description: Implementation of an ALU that supports sum/sub mul and div
Platform: | Size: 268288 | Author: Clay84 | Hits:

[VHDL-FPGA-Verilog] ALU.vhd

Description: Desarrollo de la Unidad Légica Aritmética (ALU) en VHDL
Platform: | Size: 1024 | Author: ozkkr | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[Windows Develop] ALU-ex1

Description: 计算机中执行各种算术和逻辑运算操作的部件。运算器的基本操作包括加、减、乘、除四则运算，与、或、非、异或等逻辑操作，以及移位、比较和传送等操作，亦称算术逻辑部件（ALU）。计算机运行时，运算器的操作和操作种类由控制器决定。运算器处理的数据来自存储器；处理后的结果数据通常送回存储器，或暂时寄存在运算器中。 -alu code
Platform: | Size: 176128 | Author: wenjieli | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
Platform: | Size: 169984 | Author: 李鹏飞 | Hits:

[Other] Alu

Description: 4位ALU逻辑运算器，用VHDL语言编写-4-bit ALU process using VHDL
Platform: | Size: 1024 | Author: mike | Hits:

[VHDL-FPGA-Verilog] alu

Description: mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
Platform: | Size: 4096 | Author: yzhang | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 实现加减乘除与或非和大小比较功能的ALU模块-Math and the non-realization of more functions and size of the module ALU
Platform: | Size: 1024 | Author: 唐文博 | Hits:
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