Introduction - If you have any usage issues, please Google them yourself
module alu (ina, inb, ALU_BUS, S, cout, y, clk) input [7:0] ina input [7:0] inb input ALU_BUS, clk input [2:0] S output cout output [7:0] y reg cout reg [7:0] y always @ (posedge clk) begin if (ALU_BUS) begin case (S) 3' b000: {cout, y} = ina+inb 3' b001 : {cout, y} = ina-inb 3' b010: {cout, y} = ina* inb 3' b011: {cout, y} = ina/inb 3' b100: y = ina & & inb 3' b101 : y = ina | | inb 3' b110: y = ~ inb 3' b111: y = ina ^ inb default: y = 8' b00000000 endcase end else begin y = 8' bZZZZZZZZ end end endmodule