Description: ALU implementation, the use of Veriolog language, programming, error-free, smooth build, executable, simulation plan correctly ~
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alu
...\ALU071221139.qpf
...\ALU071221139.qsf
...\ALU071221139.qws
...\ALU071221139.v
...\ALU071221139.v.bak
...\ALU071221139.vwf
...\ALU071221139_assignment_defaults.qdf
...\db
...\..\ALU071221139.db_info
...\..\ALU071221139.eco.cdb
...\..\ALU071221139.sim.cvwf
...\..\ALU071221139.sld_design_entry.sci
...\..\mux_3nc.tdf
...\..\mux_joc.tdf
...\..\prev_cmp_ALU071221139.asm.qmsg
...\..\prev_cmp_ALU071221139.fit.qmsg
...\..\prev_cmp_ALU071221139.map.qmsg
...\..\prev_cmp_ALU071221139.qmsg
...\..\prev_cmp_ALU071221139.sim.qmsg
...\..\prev_cmp_ALU071221139.tan.qmsg
...\..\wed.wsf
...\release
...\.......\ALU071221139.asm.rpt
...\.......\ALU071221139.done
...\.......\ALU071221139.fit.rpt
...\.......\ALU071221139.fit.smsg
...\.......\ALU071221139.fit.summary
...\.......\ALU071221139.flow.rpt
...\.......\ALU071221139.map.rpt
...\.......\ALU071221139.map.smsg
...\.......\ALU071221139.map.summary
...\.......\ALU071221139.pin
...\.......\ALU071221139.pof
...\.......\ALU071221139.sim.rpt
...\.......\ALU071221139.sof
...\.......\ALU071221139.tan.rpt
...\.......\ALU071221139.tan.summary
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