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VHDL-FPGA-Verilog list
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LED_Counter
Downloaded:0
this code show how to use Altium to coding LED Counter on FPGA-CPLD
Date
: 2025-07-21
Size
: 325kb
User
:
fazel
LEDglow
Downloaded:0
this code show how to use Altium to coding LED glow on FPGA-CPLD
Date
: 2025-07-21
Size
: 181kb
User
:
fazel
RS232
Downloaded:0
this code show how to use Altium to coding RS232 on FPGA-CPLD
Date
: 2025-07-21
Size
: 171kb
User
:
fazel
SEG_BUS
Downloaded:0
this code show to use Altium to coding 7 Segment BUS on FPGA-CPLD
Date
: 2025-07-21
Size
: 189kb
User
:
fazel
SW-LED
Downloaded:0
this code show to use Altium to coding Switch and LED on FPGA-CPLD
Date
: 2025-07-21
Size
: 72kb
User
:
fazel
SW-BIZ-REL
Downloaded:0
this code show to use Altium to coding Relay and Switch and Beezer on FPGA-CPLD
Date
: 2025-07-21
Size
: 57kb
User
:
fazel
SEG-1
Downloaded:0
this code show to use Altium to coding Single 7 Segment on FPGA-CPLD
Date
: 2025-07-21
Size
: 101kb
User
:
fazel
taximeter
Downloaded:0
Using VHDL, PLD design taxi billing system, using VHDL prepared Car billing system procedures, using MAX+PLUSII software as a development platform for the simulation program, designed and implemented to verify the taxi m
Date
: 2025-07-21
Size
: 541kb
User
:
zhonga
FPGA00Verilog
Downloaded:0
This file can use verilog language implementation of FPGA and computer serial port communication.
Date
: 2025-07-21
Size
: 2kb
User
:
qiuxiaohui
light
Downloaded:0
Light game based on FPGA, the whole project which includes keyboard control, SVGA and so on.
Date
: 2025-07-21
Size
: 19.57mb
User
:
YGP
fsm
Downloaded:0
verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh we
Date
: 2025-07-21
Size
: 308kb
User
:
普通场
asyn-fifo
Downloaded:0
Function is a FIFO, first in first out! To avoid the cross clock domain metastable
Date
: 2025-07-21
Size
: 183kb
User
:
zhusiwei
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