Function is a FIFO, first in first out! To avoid the cross clock domain metastable

asyn fifo
.........\db
.........\..\FIFO.db_info
.........\..\FIFO.sld_design_entry.sci
.........\..\logic_util_heursitic.dat
.........\..\prev_cmp_FIFO.qmsg
.........\FIFO.asm.rpt
.........\FIFO.done
.........\FIFO.eda.rpt
.........\FIFO.fit.rpt
.........\FIFO.fit.summary
.........\FIFO.flow.rpt
.........\FIFO.jdi
.........\FIFO.map.rpt
.........\FIFO.map.summary
.........\FIFO.pin
.........\FIFO.qpf
.........\FIFO.qsf
.........\FIFO.qws
.........\FIFO.sof
.........\FIFO.sta.rpt
.........\FIFO.sta.summary
.........\FIFO.v
.........\FIFO.v.bak
.........\fifo_ctrl.qip
.........\FIFO_nativelink_simulation.rpt
.........\greybox_tmp
.........\...........\cbx_args.txt
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\FIFO.db_info
.........\..............\README
.........\simulation
.........\..........\modelsim
.........\..........\........\FIFO.sft
.........\..........\........\FIFO.vo
.........\..........\........\FIFO.vt
.........\..........\........\FIFO.vt.bak
.........\..........\........\FIFO_7_1200mv_0c_slow.vo
.........\..........\........\FIFO_7_1200mv_0c_v_slow.sdo
.........\..........\........\FIFO_7_1200mv_85c_slow.vo
.........\..........\........\FIFO_7_1200mv_85c_v_slow.sdo
.........\..........\........\FIFO_min_1200mv_0c_fast.vo
.........\..........\........\FIFO_min_1200mv_0c_v_fast.sdo
.........\..........\........\FIFO_modelsim.xrf
.........\..........\........\FIFO_run_msim_rtl_verilog.do
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak1
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak2
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak3
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak4
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak5
.........\..........\........\FIFO_run_msim_rtl_verilog.do.bak6
.........\..........\........\FIFO_v.sdo
.........\..........\........\msim_transcript
.........\..........\........\rtl_work
.........\..........\........\........\@f@i@f@o
.........\..........\........\........\........\verilog.prw
.........\..........\........\........\........\verilog.psm
.........\..........\........\........\........\_primary.dat
.........\..........\........\........\........\_primary.dbs
.........\..........\........\........\........\_primary.vhd
.........\..........\........\........\_info
.........\..........\........\........\_temp
.........\..........\........\........\_vmake
.........\..........\........\vsim.wlf

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