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VHDL-FPGA-Verilog list
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32 carry select adder Used four carry-lookahead adder extended to 32-bit binary adder
Date : 2025-07-16 Size : 2kb User : xdx

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Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions: ADD/ADDU/SUB/SUBU/ADDI/ADDIU logic instructions shift instruction conditional branch instruction unconditional branch instruction data transfer ins
Date : 2025-07-16 Size : 20kb User : xdx

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lpc control module
Date : 2025-07-16 Size : 1kb User : logilas

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vhdl examples, including basic grammar vhdl, there are many triggers, the state machine and a small game to achieve, is to learn vhdl excellent information!
Date : 2025-07-16 Size : 53kb User : whw

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Example is a VHDL hardware description language a 38 decoder design code, FPGA chip is Aalert EPC4.
Date : 2025-07-16 Size : 1.22mb User : 金吉泉

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When this code is used to write full blog FPGA development board, the voice used is veiloge, function experiments using FPGA VGA interface hardware connections, FPGA chip ALTER EPC4
Date : 2025-07-16 Size : 7.89mb User : 金吉泉

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spdif verilog ip core
Date : 2025-07-16 Size : 12kb User : jerry

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Asynchronous FIFO memory, using Gray code determination, consume less resources
Date : 2025-07-16 Size : 1kb User : 张三

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VGA Timing Generator
Date : 2025-07-16 Size : 4kb User : jerry

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the project is complete a UART implementation where 16 UART are connect with top module for aerial applications
Date : 2025-07-16 Size : 7kb User : Naresh

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In 1602 realized characters on display! And is stitching together two 1602 displays a character! Do it yourself, run successfully!
Date : 2025-07-16 Size : 838kb User : 徐悦

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1024 points, FFT calculation eight fixed-point code refining, comprehensive notes worth downloading
Date : 2025-07-16 Size : 30kb User : 徐展
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