VHDL-FPGA-Verilog List Page 798

VHDL-FPGA-Verilog list

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SECOND Downloaded：0: FPGA-based VERILOG one second light an LED program
Date : 2025-07-22 Size : 59kb User : 杜晨婷
VGA Downloaded：0: A design for LA,use cpld to generate VGA signals.
Date : 2025-07-22 Size : 4.49mb User : yin
or_g Downloaded：0: it contains or gate, multiple input output, counter 4-bit 8 bit, parallel adder 4 -bit, 8 bit
Date : 2025-07-22 Size : 76kb User : sasbean
nn_last Downloaded：0: Neural Network with FPGA and VHDL codes + Matlab model
Date : 2025-07-22 Size : 3kb User : Zero
Rs232_Vhdl_model Downloaded：0: RS_232 VHDL model for FPGA coded
Date : 2025-07-22 Size : 11kb User : Zero
run_led Downloaded：0: Black Gold Marquee FPGA development board supporting routines, and hope to share relevant friends
Date : 2025-07-22 Size : 3.08mb User : 张哲
DDS Downloaded：0: DDS with DSP (digital signal processing), is a key digital technology. DDS is a direct digital frequency synthesizer (Direct Digital Synthesizer) abbreviation. Compared with the conventional frequency synthesizer, DDS ha
Date : 2025-07-22 Size : 686kb User : jodyql
asyn_fifo Downloaded：0: FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO , FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into
Date : 2025-07-22 Size : 635kb User : jodyql
mpi Downloaded：0: MPI interface is an interface for communication between the CPU and logic, the general way of using the bus, the bus there are two standards, one is the MOTO mode, the other one is the intel mode. This information contai
Date : 2025-07-22 Size : 120kb User : jodyql
DIFF Downloaded：0: DIFF comparing two numbers is the same number, and an identical number of outputs 5bit, output vld flag. Contains the procedures and instructions
Date : 2025-07-22 Size : 363kb User : jodyql
flow_proc Downloaded：0: In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation, the logic level signal decrease, increase frequency. The most vi
Date : 2025-07-22 Size : 224kb User : jodyql
zhl Downloaded：0: Design a Marquee controller speed can be controlled according to the external DIP switches. On the basis of the speed control, according to the display mode change Marquee external switch.
Date : 2025-07-22 Size : 369kb User :

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