Design a Marquee controller speed can be controlled according to the external DIP switches. On the basis of the speed control, according to the display mode change Marquee external switch.

Debug.fsf
Release.fsf
cmp_state.ini
db
..\divi.verilogview
..\divi1.verilogview
..\logic_util_heursitic.dat
..\prev_cmp_zhl.asm.qmsg
..\prev_cmp_zhl.fit.qmsg
..\prev_cmp_zhl.map.qmsg
..\prev_cmp_zhl.qmsg
..\prev_cmp_zhl.sim.qmsg
..\prev_cmp_zhl.tan.qmsg
..\sld_design_entry.ice
..\wed.wsf
..\zhl.asm.qmsg
..\zhl.asm.rdb
..\zhl.asm_labs.ddb
..\zhl.cbx.xml
..\zhl.cmp.cdb
..\zhl.cmp.hdb
..\zhl.cmp.kpt
..\zhl.cmp.logdb
..\zhl.cmp.rdb
..\zhl.cmp.tdb
..\zhl.cmp0.ddb
..\zhl.db_info
..\zhl.eco.cdb
..\zhl.eds_overflow
..\zhl.fit.qmsg
..\zhl.hier_info
..\zhl.hif
..\zhl.lpc.html
..\zhl.lpc.rdb
..\zhl.lpc.txt
..\zhl.map.cdb
..\zhl.map.hdb
..\zhl.map.logdb
..\zhl.map.qmsg
..\zhl.pre_map.cdb
..\zhl.pre_map.hdb
..\zhl.rtlv.hdb
..\zhl.rtlv_sg.cdb
..\zhl.rtlv_sg_swap.cdb
..\zhl.sgdiff.cdb
..\zhl.sgdiff.hdb
..\zhl.sim.cvwf
..\zhl.sim.hdb
..\zhl.sim.qmsg
..\zhl.sim.rdb
..\zhl.sim.vwf
..\zhl.sld_design_entry.sci
..\zhl.sld_design_entry_dsc.sci
..\zhl.smart_action.txt
..\zhl.syn_hier_info
..\zhl.tan.qmsg
..\zhl.tis_db_list.ddb
..\zhl.tmw_info
..\zhl_cmp.qrpt
..\zhl_sim.qrpt
incremental_db
..............\README
..............\compiled_partitions
..............\...................\zhl.root_partition.map.kpt
serv_req_info.txt
zhl.asm.rpt
zhl.bak
.......\zhl.csf
.......\zhl.psf
.......\zhl.quartus
.......\zhl.ssf
zhl.csf
zhl.csf.rpt
zhl.done
zhl.dpf
zhl.eqn
zhl.fit.eqn
zhl.fit.rpt
zhl.fit.summary
zhl.flow.rpt
zhl.map.eqn
zhl.map.rpt
zhl.map.summary
zhl.pin
zhl.pof
zhl.psf
zhl.qpf
zhl.qsf
zhl.qws
zhl.sim.rpt
zhl.sof
zhl.ssf
zhl.tan.rpt
zhl.tan.summary
zhl.v
zhl.v.bak
zhl.vwf
zhl_assignment_defaults.qdf

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