VHDL-FPGA-Verilog List Page 795

VHDL-FPGA-Verilog list

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1.6ALU-Behavioral Downloaded：0: Simple ALU behavior the way to achieve the following functions: all operations are combinational ADD/SUB on N bits operands MULTIPLY on N/2 bits operands (Least Significant Part of), result on N bits bitwise AND, OR, XOR
Date : 2025-07-16 Size : 106kb User : young
Half_Frequence Downloaded：0: The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional
Date : 2025-07-16 Size : 24kb User : qikaiyi
moore Downloaded：0: moore state machine
Date : 2025-07-16 Size : 2.85mb User : 猪妖
FPGA-multiplexer-bus Downloaded：0: Generation IV FPGA wise student boards the bus with the Quartus II project multiplexer
Date : 2025-07-16 Size : 3.01mb User : 何圣军
vganew Downloaded：0: vga code for FPGA SPARTAN 3E
Date : 2025-07-16 Size : 1.02mb User : candy
AT510-BU-98000-r0p0-00rel0 Downloaded：2: CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable information!
Date : 2025-07-16 Size : 1.17mb User : zyy
PS2mouse Downloaded：0: Application development version of PS2 mouse FPGA processing module, the main speaker mouse ps2_clk ps2_data input signal is converted to a relative displacement of the x y direction
Date : 2025-07-16 Size : 3kb User : 吴佳祥
musicplayer Downloaded：0: Using FPGA development board to do a music player that can play four simple song, you can listen through external headphones
Date : 2025-07-16 Size : 43kb User : 吴佳祥
final Downloaded：0: Fir filter stage 16, sub-module instantiation and eventually realized in the form of schematics and simulation
Date : 2025-07-16 Size : 1.25mb User : 唐江平
crc-16b-parallel Downloaded：0: CRC generator in verilog hdl
Date : 2025-07-16 Size : 1kb User : Srikanth
uart_tx Downloaded：0: uart transmitter module in verilog hdl
Date : 2025-07-16 Size : 1kb User : Srikanth
uart_rx Downloaded：0: receiver module of uart protocol in verilog hdl
Date : 2025-07-16 Size : 1kb User : Srikanth

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