CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable information!

AT510-BU-98000-r0p0-00rel0\ARM_Cortex-M0_DesignStart_ReleaseNote.pdf
..........................\AT510-BU-98000-r0p0-00rel0.lst
..........................\logical\cortexm0ds\tbench\cortexm0ds_tb.v
..........................\.......\..........\......\helloworld.c
..........................\.......\..........\......\INCA_libs\.ncv.lock
..........................\.......\..........\......\.........\cds.lib
..........................\.......\..........\......\.........\hdl.var
..........................\.......\..........\......\.........\irun.lnx86.08.20.nc\.ncrun.lock
..........................\.......\..........\......\.........\...................\.ncv.lock
..........................\.......\..........\......\.........\...................\bind.lst.lnx86
..........................\.......\..........\......\.........\...................\cds.lib
..........................\.......\..........\......\.........\...................\cdsrun.lib
..........................\.......\..........\......\.........\...................\files.ts
..........................\.......\..........\......\.........\...................\hdl.var
..........................\.......\..........\......\.........\...................\hdlrun.var
..........................\.......\..........\......\.........\...................\ncelab.args
..........................\.......\..........\......\.........\...................\ncelab.env
..........................\.......\..........\......\.........\...................\ncsim.args
..........................\.......\..........\......\.........\...................\ncsim.env
..........................\.......\..........\......\.........\...................\ncsim_restart.args
..........................\.......\..........\......\.........\...................\ncsim_restart.env
..........................\.......\..........\......\.........\...................\ncverilog.args
..........................\.......\..........\......\.........\...................\ncvlog.args
..........................\.......\..........\......\.........\...................\ncvlog.env
..........................\.......\..........\......\.........\...................\ncvlog.files
..........................\.......\..........\......\.........\...................\ncvlog.hrd
..........................\.......\..........\......\.........\snap.nc\.ncrun.lock
..........................\.......\..........\......\.........\.......\.ncv.lock
..........................\.......\..........\......\.........\.......\bind.lst.lnx86
..........................\.......\..........\......\.........\.......\cds.lib
..........................\.......\..........\......\.........\.......\cdsrun.lib
..........................\.......\..........\......\.........\.......\files.ts
..........................\.......\..........\......\.........\.......\hdl.var
..........................\.......\..........\......\.........\.......\hdlrun.var
..........................\.......\..........\......\.........\.......\ncelab.args
..........................\.......\..........\......\.........\.......\ncelab.env
..........................\.......\..........\......\.........\.......\ncsim.args
..........................\.......\..........\......\.........\.......\ncsim.env
..........................\.......\..........\......\.........\.......\ncsim_restart.args
..........................\.......\..........\......\.........\.......\ncsim_restart.env
..........................\.......\..........\......\.........\.......\ncverilog.args
..........................\.......\..........\......\.........\.......\ncvlog.args
..........................\.......\..........\......\.........\.......\ncvlog.env
..........................\.......\..........\......\.........\.......\ncvlog.files
..........................\.......\..........\......\.........\.......\ncvlog.hrd
..........................\.......\..........\......\.........\verilog\.cdsvmod
..........................\.......\..........\......\.........\.......\.inca.db.169.lnx86
..........................\.......\..........\......\.........\..

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