VHDL-FPGA-Verilog List Page 804

VHDL-FPGA-Verilog list

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vgachar Downloaded：0: VGA display characters
Date : 2025-07-22 Size : 403kb User : zhangqi
dds-veilog Downloaded：0: Both can generate various waveforms to send data through the computer, and can be set manually generate
Date : 2025-07-22 Size : 1.23mb User : 张鑫鑫
avnet_edk12_4_xbd_files Downloaded：0: Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design
Date : 2025-07-22 Size : 297kb User : 关维周
code Downloaded：0: Multi-waveform signal generator, through the FPGA to develop experimental box, you can achieve an output waveform control buttons
Date : 2025-07-22 Size : 2.01mb User : 宜露
counter Downloaded：0: measure the time period
Date : 2025-07-22 Size : 41kb User : santosh
Building-Counters-Veriog-Example Downloaded：0: building counters in vhdl
Date : 2025-07-22 Size : 15kb User : santosh
New-Text-Document Downloaded：0: mulitiplier and analog to digital
Date : 2025-07-22 Size : 1kb User : santosh
FPGA_LED Downloaded：0: NIOS II achieve control of verilogHDL contain led, schematic design, etc., directly nios II can be used to open
Date : 2025-07-22 Size : 10.9mb User : 朱阿伦
Float_add Downloaded：0: The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floati
Date : 2025-07-22 Size : 11.58mb User : zhu yue
The-four-locks-Verilog-based-design Downloaded：0: The four locks Verilog-based design, finite state machine for the preparation
Date : 2025-07-22 Size : 10kb User : 廖方颖
Verilog_UART Downloaded：0: the files use verilog HDL to realize uart.it contain reciver and transmitor.
Date : 2025-07-22 Size : 4kb User : lijie
Quartus_FPGA Downloaded：0: this a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements
Date : 2025-07-22 Size : 151kb User : takachy

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