VHDL-FPGA-Verilog List Page 809

VHDL-FPGA-Verilog list

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final-2 Downloaded：0: Digital signal system design, simulation using VHDL use of credit cards, to save money.
Date : 2025-07-21 Size : 1.05mb User : 李媛媛
hospital Downloaded：0: Digital system design, simulation hospital scenes, using VHDL language to complete the hospital' s corresponding function
Date : 2025-07-21 Size : 4.64mb User : 李媛媛
tushuguan Downloaded：0: Digital system design, simulation library scene, using VHDL complete the appropriate corresponding function library
Date : 2025-07-21 Size : 304kb User : 李媛媛
vending-machine Downloaded：0: THis a simulator of Vending Machine on Basys2 in verilog. 5jiao and 1yuan as input, 3 chioces for drinks. If all are sold out or more money is need, corresponding signals will flash on the LED screen.
Date : 2025-07-21 Size : 5kb User :
simple-pipeLine-CPU Downloaded：0: Simple pipelined CPU implementation, based on the MIPS instruction set.
Date : 2025-07-21 Size : 7kb User :
stepper-motor-control Downloaded：0: stepper motor control
Date : 2025-07-21 Size : 240kb User : chuweii
t_sensor Downloaded：0: digital temperature sensor
Date : 2025-07-21 Size : 3.2mb User : 刘昊
music Downloaded：1: A simple electronic organ function
Date : 2025-07-21 Size : 2.01mb User : 刘昊
DDS_DAC0832 Downloaded：0: DDS-based waveform generation program verilogHDL language, using AD3092 data conversion
Date : 2025-07-21 Size : 671kb User : daisy
fft_8 Downloaded：0: Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation
Date : 2025-07-21 Size : 47kb User : 王坤
_4to2 Downloaded：0: Verilog prepared based 2-wire 4-wire encoders, running directly on the board, the corresponding pin their allocation
Date : 2025-07-21 Size : 1.04mb User : maxruan
clock Downloaded：0: Based verilog digital clock source code, detailed notes, and full-featured
Date : 2025-07-21 Size : 4.12mb User : maxruan

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