VHDL-FPGA-Verilog List Page 810

VHDL-FPGA-Verilog list

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16qam Downloaded：0: implemention of 16 qam, have atlantic interfaces
Date : 2025-07-22 Size : 11kb User : 旋舞
VGA Downloaded：0: Color bar signal generator for generating and outputting color bar signal. FPGA use.
Date : 2025-07-22 Size : 287kb User : jinlu
code-pour-decim-poly Downloaded：0: this code is for a decimation filter with polyphase structure , so the original filter is decomposed by 5 filters which is the decimation factor in that case and each of them is selected each Fs/5
Date : 2025-07-22 Size : 23kb User : lassana
multiply_8_VHDL Downloaded：0: an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.
Date : 2025-07-22 Size : 3kb User : 白
60_binary_counter_vhdl_quartus2 Downloaded：0: a VHDL code of 60 binary counter and it test feasible.
Date : 2025-07-22 Size : 903kb User : 白
jiajian Downloaded：0: Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by three buttons.
Date : 2025-07-22 Size : 864kb User : 孙伟
motor2 Downloaded：0: Single and double eight four-shot pulse signal Verilog Programming stepper motor. Using 28BYJ-48 stepper motor (driver ULN2003) verification can achieve its inversion.
Date : 2025-07-22 Size : 331kb User : 孙伟
shiyan2 Downloaded：0: In other experimental procedures FPGA flow, because there is no signal generator, can not give four PWM signal generated on their own switch state signal converter used to
Date : 2025-07-22 Size : 896kb User : hufengge
SDRAM-verilog Downloaded：0: sdram co
Date : 2025-07-22 Size : 17kb User : 胡马
coinwasher2 Downloaded：0: Automatic coin washing machine controller design, including key debounce, controller module, digital display, the motor control signal output. Throw two coins will achieve half a bucket to wash, wash throw three coins to
Date : 2025-07-22 Size : 1.14mb User : shen
codeacq Downloaded：0: Spread spectrum communication system code synchronization. Application vhdl language, you can run
Date : 2025-07-22 Size : 1.4mb User : 黄培哲
CRC Downloaded：0: CRC source code, FPGA-based development environment source code.
Date : 2025-07-22 Size : 9kb User : tiercel

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