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Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
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Size: 120832 |
Author: 杰轩 |
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Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
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Size: 122880 |
Author: zlin |
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Description: 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
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Size: 1024 |
Author: 李向坤 |
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Description: 基于s3c24140的arm920t的PLL编程，希望对广大朋友有帮助。-s3c24140 arm920t PLL programming, and I hope to help the broad masses of friends.
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Size: 4096 |
Author: 王剑 |
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Description: 二阶锁相环Matlab仿真代码，如入两路信号和信噪比，输出锁相以后的信号。可以仿真初始频差，和频率斜升的情况-second-order PLL Matlab simulation code, such as two-way signals and signal to noise ratio, the output signal after the lock-in. Simulation can initial frequency difference, and frequency ramp-up of
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Size: 2048 |
Author: 里根 |
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Description: Excel spreadsheet allowing calculation of the best R-C-C component values on the PLL Loop Back Filter. -Excel spreadsheet allowing calculation o the best f R-C-C component values on the Loop PLL Back Filter.
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Size: 459776 |
Author: 张爽 |
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Description: 锁相环设计文档和一个可执行文件-PLL design documents and an executable file
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Size: 108544 |
Author: KC_P |
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Description: 简单的可配置dpll的VHDL代码。
用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
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Size: 2048 |
Author: 陈德炜 |
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Description: cyclone上的PLL使用教材。好多人要得。-cyclone on the use of the PLL materials. Many people fine.
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Size: 553984 |
Author: cyj |
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Description: C51的基于KST-CD111LVD-100 car tuner Driver PLL LC72131 & LA1787 的数字调谐系统-C51-based DRAM-CD111LVD-100 car tuner Driver PLL LC72131
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Size: 6144 |
Author: tonychen |
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Description: 本源程序使用C51控制的PLL(SANYO LC72131)收音,可以通过HT1621驱动LCD显示,有完整的按键控制程序模块,能通过KEY进行各种功能操作,整个程序采用模块化设计,移植方便,可以初学者参考使用.(之前的那个也是我上载的,怎么就没开通?)-C51 use the source control PLL (SANYO LC72131) radio, Driving through HT1621 LCD Display, a complete module button control procedures, KEY through various functional operation, the whole process has a modular design and facilitate transplantation, beginners can use and reference. (which is also before I posted, how never opened)
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Size: 675840 |
Author: 李先生 |
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Description: 一本介绍pll的书籍，讲了它的原理，几个重要的指标参数以及几种结构种类。-pll a briefing books, it stresses the principle, a number of important parameters and the structure of several types.
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Size: 1129472 |
Author: 施耀华 |
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Description: 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
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Size: 1024 |
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Description: 用一阶锁相环实现的FM解调器.用ELANIX公司的SYSTEMVIEW运行调试.-with a band of PLL FM demodulator. ELANIX company with the SYSTEMVIEW Win OK debugging.
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Size: 1024 |
Author: a |
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Description: 直接式数字锁相环频率合成器.用ELANIX公司SYSTEMVIEW运行.-direct digital PLL frequency synthesizer. SYSTEMVIEW ELANIX companies with operations.
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Size: 1024 |
Author: a |
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Description: 本程序是一个PLL仿真程序，分为参数设置，仿真和后显示三部分.-this procedure is a PLL simulation program, is divided into parameters, simulation and revealed three parts.
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Size: 2048 |
Author: ltj1974 |
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Description: 这个程序是matlab用来来对锁相环（PLL）进行仿真的，这样的选择基于多方面的考虑-This procedure is used Matlab to the phase-locked loop (PLL) simulation, This choice is based on a number of considerations
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Size: 1024 |
Author: lizhihui |
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Description: 模块使用外部滤波器回路来抑制信号抖动和电磁干扰。滤波器回路由PLL接在滤波器输入引脚PLLF和PLLF2之间的电阻Rl和电容Cl、C2组成。电容 Cl、C2必须为无极性电容。在不同的振荡器频率下，R1、Cl、C2的取值不同，常用的参数组合如表l所列。PLL模块的电源引脚PLLVCCA分别通过磁珠和0.1μF的电容与数字电源引脚VDD和数字地引脚VSS连接，构成低通滤波电路，保证时钟模块的可靠供电。模块使用外部滤波器回路来抑制信号抖动和电磁干扰。滤波器回路由PLL接在滤波器输入引脚PLLF和PLLF2之间的电阻Rl和电容Cl、C2组成。电容 Cl、C2必须为无极性电容。在不同的振荡器频率下，R1、Cl、C2的取值不同，常用的参数组合如表l所列。PLL模块的电源引脚PLLVCCA分别通过磁珠和0.1μF的电容与数字电源引脚VDD和数字地引脚VSS连接，构成低通滤波电路，保证时钟模块的可靠供电。-err
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Size: 1024 |
Author: eric |
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Description: PLL-LMX2325 C程序,用于锁相环频率控制-PLL-LMX2325 C procedures for the PLL frequency control
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Size: 1024 |
Author: 千里沙鸥 |
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Description: 三星的有关ARM9的S3C 系列的PLL频率设置软件，ARM开发中可以快速设置所需要的频率参数-Samsung's S3C the ARM9 series of PLL installed software, ARM development can quickly set up the required frequency parameters
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Size: 93184 |
Author: 毛斌 |
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