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Description: A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
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Size: 236523 |
Author: 谢振 |
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Description: pll 的一段吗狄梵思黛发的发射点法 的发射点法
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Size: 1455 |
Author: sai |
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Description: 附件里的代码，里面有详细过程说明：
Phasell.m
pll.m
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Size: 7216 |
Author: mzb |
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Description: 关于在FPGA或CPLD锁相环PLL原理与应用,介绍用FPGA的分频技术.
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Size: 94071 |
Author: yjc |
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Description: pll算法是来自经典的DSP的C程序和汇编程序库
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Size: 128403 |
Author: dsp |
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Description: PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形
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Size: 807196 |
Author: 许东滨 |
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Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！
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Size: 352799 |
Author: li |
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Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
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Size: 111853 |
Author: 孙犁 |
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Description: An enhanced phase-locked loop (PLL) system is presented
and its properties and performance characteristics
are investigated. Advantages of the proposed PLL
structure over the conventional PLLs including its capability of direct estimation of amplitude and phase angle of its input signal, within a wide range of parameters,are demonstrated. Main features of the proposed PLL are structural simplicity and performance robustness. Performance of the PLL, based on both analog and digital realization, is also presented.
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Size: 418825 |
Author: yangyansky |
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Description: 程序模拟了pll中PFD,VCO,CP,LOOP-FILTER等各部分的噪声性能，并进行整个链路的仿真优化，仅供参考。
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Size: 1124 |
Author: huokedu@yahoo.com.cn |
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Description: verilog写的数字PLL
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Size: 3515 |
Author: jinhfut@163.com |
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Description: verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
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Size: 383668 |
Author: sakajj |
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Description: 锁相环PLL原理与应用
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Size: 93856 |
Author: lislea |
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Description: lattice的PLL模块实现，以及verilog的实现
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Size: 752 |
Author: mojianshusheng |
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Description: LC72131 PLL C源程序-LC72131 PLL C source
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Size: 4096 |
Author: hehe |
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Description: LC72131 PDF-Sanyo PLL chip LC72131 datasheet.
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Size: 343040 |
Author: nana |
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Description: C语言程序,LC72131+PIC16C63+PT2258 -C source code for Sanyo LC72131 PLL radio using PIC16C63 as MCU for 3 wires bus control and Digital Volume Controller IC PT2258.
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Size: 5120 |
Author: |
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Description: BU2614 PLL 源程序,直接解压-source code for digital tuning system using BU2614 PLL IC. Please unzip directly.
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Size: 10240 |
Author: 蒋江黔 |
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Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
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Size: 124928 |
Author: 于洪彪 |
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Description: 锁相环程序，用MATLAB 编写，用来防真琐相环的工作过程。有学习价值-A PLL S PROGRAM CODING IN MATLAB,WHICH CAN SIMULATE THE PROCESS OF PLL.IT S VALUABE FOR LEARNING
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Size: 2048 |
Author: luke |
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