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Description: MB1504锁相环芯片的51单片机驱动程序,可以根据需要修改合适的分频值来完成频率合成配置.-MB1504 PLL chip 51 Single-chip driver, need to be amended in accordance with the appropriate value of the sub-band frequency synthesizer to complete the configuration.
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Size: 10240 |
Author: 魏广寅 |
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Description: This project allows you to learn communication systems in greater depth. It contains the Simulink files (*.mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation.
The idea here is to implement experiments of a traditional communication lab using Simulink.
Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories-This project allows you to learn communication systems in greater depth. It contains the Simulink files (*. mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional communication lab using Simulink.Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories
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Size: 2468864 |
Author: haibak |
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Description: DSP启动时接口配置文件，包括DDR，Pll，GPIO等部分-DSP interface startup configuration file, including DDR, Pll, GPIO and other parts of
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Size: 2048 |
Author: wanghb |
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Description: DSP2808例程。TMS320F2808DSP的各个模块的应用例程，包括SCI，PWM，AD，CAN，PLL等-DSP2808 routines. TMS320F2808DSP the various modules of the application of routines, including the SCI, PWM, AD, CAN, PLL, etc.
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Size: 2957312 |
Author: chenjingan |
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Description: 锁相环PLL原理及应用，请需要的朋友下载-PLL phase-locked loop principle and application, please download the Friend in need
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Size: 91136 |
Author: 磊 |
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Description: 基于ADF4001的锁相环程序，AVR GCC版本。所用单片机为ATMEGA16L-ADF4001 PLL-based procedures, AVR GCC version. Used ATMEGA16L singlechip
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Size: 22528 |
Author: 柴源 |
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Description: 8051单片机结合BU2614的PLL程序，并由普通遥控器进行操作。-BU2614 combining 8051 the PLL procedures, by an ordinary remote control to operate.
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Size: 58368 |
Author: 陈敏 |
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Description: 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化，基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。因此，该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境；同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。-Introduce an approach based on frequency-locking phase-locked loop (FPLL) carrier tracking algorithm. Frequency tracking module can adapt to a larger dynamic range of the frequency change, software-based numerical control oscillator (NCO) module can achieve the very high frequency tracking accuracy. Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. Therefore, the FPLL carrier-based tracking algorithm can be adapted to signal the existence of a larger dynamic range and noise of the application environment at the same time, the PFD algorithm expression is simple, easy to use programmable digital devices.
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Size: 162816 |
Author: 何宁 |
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Description: TI DM648 PLL配置源代码,可以下接下到板子上,非常不错-TI DM648 PLL configuration source code, you can take to the board on the next, very good
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Size: 4096 |
Author: 张健 |
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Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
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Size: 178176 |
Author: 冯勇 |
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Description: fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
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Size: 8192 |
Author: wq |
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Description: 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
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Size: 3802112 |
Author: xin |
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Description: PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code-PLL system LPF/PFD/VCO/Divider model in Matlab, the Matlab will PLL system model of each module, the easy analysis of the whole PLL loop stability characteristics, lock time ... ... the appendix contains a complete Matlab code
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Size: 92160 |
Author: xin |
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Description: 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
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Size: 14336 |
Author: 张景英 |
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Description: Ph.D thesis from M.H.Perrott, about Fractional-N PLL design.
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Size: 4283392 |
Author: ge binjie |
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Description: PhD.thesis about fractional PLL design from UC san-deago.
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Size: 778240 |
Author: ge binjie |
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Description: LPC23xx系列ARM时钟源的选择、PLL的设置步骤以及注意事项等。PPT做的非常出色。-LPC23xx Series ARM clock source selection, PLL settings, as well as attention to matters such as these. PPT doing very well.
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Size: 422912 |
Author: 徐志江 |
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Description: Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
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Size: 1024 |
Author: 曾捷 |
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Description: 1、数字锁相环的单片机代码。
2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
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Size: 11264 |
Author: foxmail2008 |
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Description: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
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Size: 1275904 |
Author: Donghua Gu |
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