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[VHDL-FPGA-Verilog] 16bit_pipeline

Description: 16 bit pipeline design by vhdl.
Platform: | Size: 318464 | Author: leejp | Hits:

[Graph program] ADCtestprogram

Description: adc 的测试程序,测试adc的各种静态和动态特性。-the testing program of pipeline adc
Platform: | Size: 9216 | Author: 史小凤 | Hits:

[Other] es_full_spec.1.1.12

Description: 在移动设备上开发OpenGl|ES的书籍，此书比较详细的介绍了OpenGL|ES的标准，并按照渲染管线的流程一一介绍。-On mobile devices developed OpenGl | ES books, book more detailed introduction to the OpenGL | ES standard and in accordance with the process of rendering pipeline 11 introduction.
Platform: | Size: 777216 | Author: 于哲 | Hits:

[VHDL-FPGA-Verilog] arm7

Description: ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline
Platform: | Size: 173056 | Author: hcq | Hits:

[Embeded-SCM Develop] pipelinePHD

Description: 大师Gray和Allen学生pipeline phd 论文（超经典）和razavi 的adc书-Gray and Allen Masters student pipeline phd thesis (Ultra Classic), and the adc book razavi
Platform: | Size: 6998016 | Author: suborong | Hits:

[Database system] 2004111216177413

Description: 用PB9做的一个管理代码的助手型工具，启动自注册ODBC，除了对正常的代码进行管理外，还采用了OLE 2.0技术存储所有格式的文件（其实常用的只有Office和压缩文件），具有每日提醒功能和会议提醒，利用数据管道技术进行数据库自身的整理（可减小数据库文件体积）。程序还有很多Bug，欢迎大家提意见啊。 -PB9 to do with an assistant-based tool for managed code, launch self-registration ODBC, in addition to the normal management of the code, but also uses OLE 2.0 technology stores all file formats (which is used only Office and compressed files), with each of reminded function and meeting reminders, using data pipeline technology for the collation of the database itself (which can reduce the database file size). There are many procedures Bug, welcome comments ah.
Platform: | Size: 473088 | Author: ywend123 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: 32 bit RISC Processor with 3 stage pipeline
Platform: | Size: 2152448 | Author: rudra | Hits:

[VHDL-FPGA-Verilog] Cordic123

Description: for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
Platform: | Size: 109568 | Author: jai | Hits:

[VHDL-FPGA-Verilog] post_norm_mul

Description: 符合IEEE754标准的32位浮点流水线乘法器 采用移位相加算法，-32-bit floating point pipeline multiplier on IEEE754 standard
Platform: | Size: 3072 | Author: Thomas | Hits:

[Other Embeded program] pipeline_ADC_PLL

Description: 该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较 器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为 1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8 V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结 果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·- verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin— Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV， the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18 um technology demonstrate its effectiveness．
Platform: | Size: 361472 | Author: 赵恒 | Hits:

[VHDL-FPGA-Verilog] processor

Description: processor design istruction load pipeline ,hazard
Platform: | Size: 41984 | Author: oiwehfoiwaefhp | Hits:

[Other] Pipeline

Description: 给定n 口油井的位置,编程计算各油井到主管道之间的输油管道最小长度总-find the nearest distance from all the oil field to the pipeline.
Platform: | Size: 2161664 | Author: smart_hh | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[Other] PipelineCPU

Description: Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
Platform: | Size: 847872 | Author: znl | Hits:

[source in ebook] Pipeline

Description: 程序解决了给定油井位置，求出一条东西向输油管道的位置，使之到各个油井的距离之和达到最小 //程序一次性读入11组测试文件，将油井纵坐标存储在动态开辟的pipey数组里，通过运用在数组中查找第K小个元素的算法找到了管道的最优位置 //最后求得最短距离后，将最终结果一次性存储到11个输出文件中。-Program to solve a given oil well location, find a location east-west pipeline, so that the distance to each well and achieve the minimum// process into 11 groups of one-time reading test file, will store well in a dynamic open up the vertical axis of pipey array, through the use of the array to find the first K elements of the algorithm for small to find the optimal location of pipeline// Lastly, after the shortest distance obtained, once the final results will be stored in the output file 11.
Platform: | Size: 2048 | Author: 秦文煜 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[matlab] multicoil

Description: 石油管道环境下超长波发射器的电磁场建模，用于描述管道环境，包含边界条件。-Oil pipeline under long wave electromagnetic field transmitter model, used to describe the pipeline environment, including boundary conditions.
Platform: | Size: 1024 | Author: 张也 | Hits:
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