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Description: 计算机体系结构中关于通用5级流水线的模拟实现程序-computer architecture on the common five Pipeline Simulation procedures
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Size: 422123 |
Author: 欧未然 |
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Description: 一个模拟管道流动的ACTIVEX控件-a simulated pipeline flow ACTIVEX control
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Size: 44032 |
Author: 刘明法 |
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Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
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Size: 5120 |
Author: 刘陆陆 |
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Description: mips pipeline 模以程序，mfc实现的，功能就不用说了把，大家都知道的-MIPS pipeline to die procedures mfc achieve, and functions not have had to put, we all know the
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Size: 24576 |
Author: 吴动 |
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Description: 一个三维gis管线的源代码
做三维管线gis的开发人员可以参考下-a 3D pipeline gis the source code to do 3D pipeline gis developers can refer to the next
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Size: 545792 |
Author: 王涛 |
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Description: 推荐下载,verilog状态机实例.体现了流水线思想的应用
-recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
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Size: 2048 |
Author: 陶玉辉 |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
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Size: 179200 |
Author: 李中伟 |
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Description: vxworks 下多线程编程事例代码
包括：管道，队列，信号，多线程-vxworks multi-threaded programming code examples include : pipeline, queue, signals, multithreading
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Size: 28672 |
Author: |
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Description: 采用ANSYS软件的APDL语言编写的两个命令流文件，用于计算含缺陷管道的失效概率，将参数稍作改动，可用于其它结构的可靠性分析-using ANSYS APDL preparation of the two documents order flow, used in the calculation of pipeline containing defects failure probability of parameters minor modifications, can be used for other structural reliability analysis
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Size: 3072 |
Author: 文尧 |
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Description: pb数据管道,可以选择要上传的表,实现多表连续上传.-pb data pipeline, we can choose to upload tables, multi-row table uploads.
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Size: 44032 |
Author: 东方神猫 |
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Description: 管道技术，利用管道实现两个进程数据交换，包含事件消息-pipeline technology, the use of two pipelines achieving data exchange processes, including news events
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Size: 67584 |
Author: 张少华 |
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Description: Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between synchronous and asynchronous systems, or between
synchronous systems operating from different clocks.-Pipeline synchronization is a simple, low-cost, highbandwidth. highreliability solution to interfaces betwe en synchronous and asynchronous systems, or between synchronous systems operating from different clocks.
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Size: 855040 |
Author: 叶艳 |
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Description: 主要介绍算法的实现方式和流水线实现，而且有详细的原理介绍，推理，源码和仿真结果-The main way of introduction Algorithm and pipelining to achieve, but also has a detailed introduction of the principle, reasoning, source code and simulation results
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Size: 162816 |
Author: 李佳 |
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Description: 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
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Size: 2048 |
Author: wgx |
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Description: 介绍C#的管道技术，实现程序之间的通讯。在Microsoft Visual Studio 2005 下编译通过。值得借鉴-Introduced the C# Pipeline technology, communication between procedures. In the next Microsoft Visual Studio 2005 compiler through. Worth learning
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Size: 248832 |
Author: aq |
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Description: samples for pipe line source code
-samples for pipe line source code
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Size: 8192 |
Author: 陳陳 |
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Description: 8 bit multiplier with pipeline design, mainly for studying and learning purpose
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Size: 1024 |
Author: q |
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Description: 输油管道问题，用文件的方式，用的是分而治之的思想-Pipeline problems, and use of papers, using a divide and rule ideology
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Size: 230400 |
Author: kobewylb |
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Description: 2767 管道连接的游戏. 个人觉得做的不错. 很耐玩,不下是损失-2767 pipeline game. Personally feel that to do well. Very Nai Wan, is no less than loss
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Size: 189440 |
Author: 王先生 |
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Description: cordic IP core
Features
Each file is stand-alone and represents a specific configuration.
The 4 parameters are:
Rotation or Vector Mode
Vector Precision
Angle Precision
Number of Cordic Stages
All designs are pipelined with a synchronous enable and reset.
The pipeline latency equals 2 clock cycles plus the number of cordic stages.
The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v
r : Cordic Mode. r = Rotation, v = Vectoring
32 : Precision of the individual vector components.
16 : Precision of the angle.
12 : Number of cordic stages.
Current configurations:
cf_cordic_r_8_8_8
cf_cordic_v_8_8_8
cf_cordic_r_16_16_16
cf_cordic_v_16_16_16
cf_cordic_r_18_18_18
cf_cordic_v_18_18_18
cf_cordic_r_32_32_32
cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
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Size: 457728 |
Author: abcoabco |
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